公开(公告)号：DE60334835D1

公开(公告)日：2010-12-16

申请号：DE60334835

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F13/24

公开(公告)号：DE60327362D1

公开(公告)日：2009-06-04

申请号：DE60327362

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/46 ,  G06F9/48 ,  G06F12/00

Abstract: A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing process states for that processor to the memory, independent of the operating system running on the processor.

公开(公告)号：AT329316T

公开(公告)日：2006-06-15

申请号：AT02749086

申请日：2002-07-25

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  GUTHRIE GUY LYNN ,  JOYNER JODY BERN ,  LEWIS JERRY DON

IPC: H04L12/42 ,  G06F15/17 ,  G06F15/173

Abstract: The symmetric multiprocessor system includes multiple processing nodes, with multiple agents at each node, connected to each other via an interconnect. A request transaction is initiated by a master agent in a master node to all receiving nodes. A write counter number is generated for associating with the request transaction. The master agent then waits for a combined response from the receiving nodes. After the receipt of the combined response, a data packet is sent from the master agent to all intended one of the receiving nodes according to the combined response. After the data packet has been sent, the master agent in the master node is ready to send another request transaction along with a new write counter number, without the necessity of waiting for an acknowledgement from the receiving node.

公开(公告)号：CA2508551A1

公开(公告)日：2004-06-17

申请号：CA2508551

申请日：2003-11-14

Applicant: IBM

Inventor： GUTHRIE GUY LYNN ,  CARGNONI ROBERT ALAN ,  STARKE WILLIAM JOHN ,  ARIMILLI RAVI KUMAR

IPC: G06F9/22 ,  G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A method and system are disclosed for saving soft state information, which i s non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memor y associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan - chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

公开(公告)号：CA2508041A1

公开(公告)日：2004-06-17

申请号：CA2508041

申请日：2003-11-14

Applicant: IBM

Inventor： STARKE WILLIAM JOHN ,  ARIMILLI RAVI KUMAR ,  GUTHRIE GUY LYNN ,  CARGNONI ROBERT ALAN

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F13/24

Abstract: A method and system are disclosed for pre-loading a hard architected state o f a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stor ed in the processor, are determined based on priorities assigned to the waiting processes.

公开(公告)号：PL333006A1

公开(公告)日：1999-11-08

申请号：PL33300697

申请日：1997-09-30

Applicant: IBM

Inventor： GUTHRIE GUY LYNN ,  NEAL DANNY MARVIN ,  KELLEY RICHARD ALLEN

IPC: G06F13/40

Abstract: A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter, residing within a Host Bridge, Control & Power logic, and a plurality of in-line switch modules coupled to a bus. Each of the in-line switch modules provide isolation for load(s) connected thereto. The Host Bridge in combination with the Control & Power Logic implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).

公开(公告)号：GB2334120A

公开(公告)日：1999-08-11

申请号：GB9909356

申请日：1997-09-30

Applicant: IBM

Inventor： GUTHRIE GUY LYNN ,  NEAL DANNY MARVIN ,  KELLEY RICHARD ALLEN

IPC: G06F13/40 ,  G06F1/00

Abstract: A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter (202a), residing within a Host Bridge (202), Control and Power Logic (208), and a plurality of in-line switch modules (326, 328) coupled to a bus. Each of the in-line switch modules (326, 328) provides isolation for load(s) connected thereto. The Host Bridge (202) in combination with the Control and Power Logic (208) implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).