公开(公告)号：IT8819946D0

公开(公告)日：1988-03-25

申请号：IT1994688

申请日：1988-03-25

Applicant: IBM

Inventor： CONCILIO IAN A ,  HAWTHORNE JEFFREY A ,  HEATH CHESTER ASBURY ,  LENTA JORGE EDUARDO ,  NGUYEN LONG D

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/362 ,  G06F13/374

Abstract: A computer system is coupled to peripherals having their own DMA channel arbiter and peripherals having no arbiter. A separate arbitration unit, controlled directly by the CPU, is provided to arbitrate on behalf of peripherals having no arbiter. The CPU can thus freely assign different arbitration levels to such peripherals, and can instruct the arbitration unit to simultaneously arbitrate on different arbitration levels or for two or more DMA channels.

公开(公告)号：IT8819827D0

公开(公告)日：1988-03-18

申请号：IT1982788

申请日：1988-03-18

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  LENTA JORGE EDUARDO

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/362 ,  G06F13/374 ,  G06F

Abstract: A computer system in which peripherals greater in number than the number of DMA channels provided in the system can all have DMA access. Some of the DMA channels are dedicated to certain ones of the peripherals, while others are shared by remaining ones of the peripherals. Each peripheral having DMA access has a channel priority value. When a peripheral wants DMA access, it transmits its channel priority value onto an arbitration bus. The winning channel priority value is then compared with prestored DMA channel assignment values. If the comparison is successful, the corresponding peripheral is given a DMA channel corresponding to the DMA channel assignment value with which the comparison was successful.

公开(公告)号：DK135888D0

公开(公告)日：1988-03-11

申请号：DK135888

申请日：1988-03-11

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  LANGGOOD JOHN KENNEDY ,  VALLI RONALD EUGENE

IPC: G06F1/00 ,  G06F1/18 ,  G06F13/14 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00 ,  G06F12/00 ,  G06F13/00

Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.

公开(公告)号：IN178181B

公开(公告)日：1997-03-08

申请号：IN49DE1988D

申请日：1988-01-20

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  LANGGOOD JOHN KENNEDY ,  VALLI RONALD EUGENE

IPC: G06K21/00

公开(公告)号：FI93585C

公开(公告)日：1995-04-25

申请号：FI880656

申请日：1988-02-12

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  LANGGOOD JOHN KENNEDY ,  VALLI RONALD EUGENE

IPC: G06F1/00 ,  G06F1/18 ,  G06F13/14 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00

公开(公告)号：DK169366B1

公开(公告)日：1994-10-10

申请号：DK135888

申请日：1988-03-11

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  LANGGOOD JOHN KENNEDY ,  VALLI RONALD EUGENE

IPC: G06F1/00 ,  G06F1/18 ,  G06F1/24 ,  G06F13/14 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00 ,  G06F13/10

Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.

公开(公告)号：DE3881414D1

公开(公告)日：1993-07-08

申请号：DE3881414

申请日：1988-03-08

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  LANGGOOD JOHN KENNEDY ,  VALLI RONALD EUGENE

IPC: G06F13/14 ,  G06F1/00 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00

Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.

公开(公告)号：IN172332B

公开(公告)日：1993-06-19

申请号：IN178DE1988

申请日：1988-08-09

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  LENTA JORGE EDUARDO

IPC: G06F15/00

公开(公告)号：DE3782045T2

公开(公告)日：1993-04-15

申请号：DE3782045

申请日：1987-12-15

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  LENTA JORGE EDUARDO

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/362 ,  G06F13/374

Abstract: A computer system in which peripherals greater in number than the number of DMA channels provided in the system can all have DMA access. Some of the DMA channels are dedicated to certain ones of the peripherals, while others are shared by remaining ones of the peripherals. Each peripheral having DMA access has a channel priority value. When a peripheral wants DMA access, it transmits its channel priority value onto an arbitration bus. The winning channel priority value is then compared with prestored DMA channel assignment values. If the comparison is successful, the corresponding peripheral is given a DMA channel corresponding to the DMA channel assignment value with which the comparison was successful.

公开(公告)号：NZ223454A

公开(公告)日：1992-09-25

申请号：NZ22345488

申请日：1988-02-09

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  LANGGOOD JOHN KENNEDY ,  VALLI RONALD EUGENE

IPC: G06F1/00 ,  G06F1/18 ,  G06F1/24 ,  G06F13/14 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00 ,  G06F13/00 ,  G06F11/00

Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.