公开(公告)号：DE3880750T2

公开(公告)日：1993-10-28

申请号：DE3880750

申请日：1988-05-20

Applicant: IBM

Inventor： HWANG WEI ,  LU NICKY C

IPC: H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94 ,  H01L21/82

Abstract: A semiconductor memory cell structure incorporating a vertical access transistor over a trench storage capacitor including a semiconductor wafer having a semiconductor substrate (16) and an epitaxial layer (36) disposed thereon. A relatively deep polysilicon filled trench (26) is disposed in the epitaxial layer and substrate structure, the deep trench (26) having a composite oxide/nitride insulation layer (24) over its vertical and horizontal surfaces to provide a storage capacitor insulator. A relatively shallow trench is disposed in the epitaxial layer (36) over the deep trench (26) region, the shallow trench having an oxide insulation layer (46) on its vertical and horizontal surfaces thereof. A neck structure (34) of epitaxial polysilicon material extends from the top surface of the polysilicon filled deep trench (26) to the bottom surface of the shallow trench. Impurities are disposed in the epitaxial layer (36) on either side of the shallow trench to form semiconductor device drain (40) junctions and polysilicon material (48) is disposed in the shallow trench and over the epitaxial layer (36) to form semiconductor device transfer gate and wordline regions respectively.

公开(公告)号：DE3785317T2

公开(公告)日：1993-10-28

申请号：DE3785317

申请日：1987-11-24

Applicant: IBM

Inventor： HWANG WEI ,  SCHUSTER STANLEY EVERETT ,  TERMAN LEWIS MADISON

IPC: G11C11/401 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/82

Abstract: A vertical DRAM structure comprising a VMOS transistor and trench capacitor in combination wherein the access transistors are in a V-groove and the capacitors are in two vertical layers. The structure has only a single level of polysilicon and has no contacts. The memory cell circuit is a one-device memory cell, having a single access transistor with its gate (40) connected to a word line (WL), its drain (30) connected to a bit line (BL), and its source (22) connected to a storage capacitor. More particularly, the storage capacitance node (16) is connected to the source (22) of the V-groove access device through a conducting bridge (e.g. 18). An epitaxial layer (26) is grown over a combination of single crystalline material and oxide. Polycrystalline regions in the silicon substrate have an oxide covering. In an alternate version, a single crystal epitaxial layer is disposed over regions consisting of both single crystal and poly crystal Si or polycrystalline material on top of single crystalline material is converted into single crystalline material.

公开(公告)号：DE3785317D1

公开(公告)日：1993-05-13

申请号：DE3785317

申请日：1987-11-24

Applicant: IBM

Inventor： HWANG WEI ,  SCHUSTER STANLEY EVERETT ,  TERMAN LEWIS MADISON

IPC: G11C11/401 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/82

Abstract: A vertical DRAM structure comprising a VMOS transistor and trench capacitor in combination wherein the access transistors are in a V-groove and the capacitors are in two vertical layers. The structure has only a single level of polysilicon and has no contacts. The memory cell circuit is a one-device memory cell, having a single access transistor with its gate (40) connected to a word line (WL), its drain (30) connected to a bit line (BL), and its source (22) connected to a storage capacitor. More particularly, the storage capacitance node (16) is connected to the source (22) of the V-groove access device through a conducting bridge (e.g. 18). An epitaxial layer (26) is grown over a combination of single crystalline material and oxide. Polycrystalline regions in the silicon substrate have an oxide covering. In an alternate version, a single crystal epitaxial layer is disposed over regions consisting of both single crystal and poly crystal Si or polycrystalline material on top of single crystalline material is converted into single crystalline material.

公开(公告)号：AU609167B2

公开(公告)日：1991-04-26

申请号：AU2033688

申请日：1988-08-02

Applicant: IBM

Inventor： HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: H01L27/10 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/78 ,  H01L21/82 ,  H01L29/94

Abstract: A new high density vertical trench transistor and trench capacitor DRAM (dynamic-random-access memory) cell is described incorporating a wafer with a semiconductor substrate (10) and an epitaxial layer (10) thereon including a vertical transistor (14) disposed in a shallow trench (100) stacked above and self-aligned with a capacitor in a deep trench (16). The stacked vertical transistor (4) has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. The drain of the access transistor (14) is a lightly-doped drain structure (21) connected to a bitline element (22). The source (24) of the transistor, located at the bottom of the transistor trench (100) and on top of the center of the trench capacitor (16), is self-aligned and connected to polysilicon (28) contained inside the trench capacitor. Three sidewalls of the access transistor (14) are surrounded by thick oxide isolation (50) and the remaining one side is connected to drain and bitline contacts. The memory cell is located inside an n-well (26) and uses the n-well and heavily-doped substrate (10) as the capacitor counter-electrode plate. The cell storage node is the polysilicon (28) inside the trench capacitor. The fabrication method includes steps for growing epitaxial layers wherein an opening (100) is left which serves as the shallow trench access transistor region and provides self-alignment with the deep trench storage capacitor.