公开(公告)号：DE69430973T2

公开(公告)日：2003-02-13

申请号：DE69430973

申请日：1994-09-08

Applicant: IBM

Inventor： KAHLE JAMES ALLAN

IPC: G06F9/312 ,  G06F9/38 ,  G06F12/08

Abstract: An information processing system 10 includes a processor 10 for processing instructions, a system memory 30, a cache memory 12, and a supplemental 26. In response to a first instruction, the supplemental memory stores first information from a system memory. In response to a second instruction, the cache memory stores second information from the supplemental memory if the first information includes the second information and from the system memory otherwise.

公开(公告)号：DE68927911T2

公开(公告)日：1997-09-18

申请号：DE68927911

申请日：1989-12-20

Applicant: IBM

Inventor： GROHOSKI GREGORY FREDERICK ,  KAHLE JAMES ALLAN ,  NGUYENPHU MYHONG ,  RAY DAVID SCOTT

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48 ,  G06F9/46

Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

公开(公告)号：DE68927911D1

公开(公告)日：1997-04-30

申请号：DE68927911

申请日：1989-12-20

Applicant: IBM

Inventor： GROHOSKI GREGORY FREDERICK ,  KAHLE JAMES ALLAN ,  NGUYENPHU MYHONG ,  RAY DAVID SCOTT

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48 ,  G06F9/46

Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

公开(公告)号：AU618142B2

公开(公告)日：1991-12-12

申请号：AU4433789

申请日：1989-11-02

Applicant: IBM

Inventor： GROHOSKI GREGORY FREDERICK ,  RAY DAVID SCOTT ,  NGUYENPHU MYHONG ,  KAHLE JAMES ALLAN

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48

Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

公开(公告)号：GB2227108A

公开(公告)日：1990-07-18

申请号：GB8928776

申请日：1989-12-20

Applicant: IBM

Inventor： GROHOSKI GREGORY FREDERICK ,  KAHLE JAMES ALLAN ,  NGUYENPHU MYHONG ,  RAY DAVID SCOTT

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48

Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.