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    6.
    发明专利
    未知

    公开(公告)号：BR9000112A

    公开(公告)日：1990-10-23

    申请号：BR9000112

    申请日：1990-01-12

    Applicant: IBM

    Inventor： GROHOSKI GREGORY FREDERICK ,  KAHLE JAMES ALLAN ,  NGUYENPHU MYHONG ,  RAY DAVID SCOTT

    IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48 ,  G06F15/80

    Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

    7.
    发明专利
    未知

    公开(公告)号：DE68927911T2

    公开(公告)日：1997-09-18

    申请号：DE68927911

    申请日：1989-12-20

    Applicant: IBM

    Inventor： GROHOSKI GREGORY FREDERICK ,  KAHLE JAMES ALLAN ,  NGUYENPHU MYHONG ,  RAY DAVID SCOTT

    IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48 ,  G06F9/46

    Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

    8.
    发明专利
    未知

    公开(公告)号：DE68927911D1

    公开(公告)日：1997-04-30

    申请号：DE68927911

    申请日：1989-12-20

    Applicant: IBM

    Inventor： GROHOSKI GREGORY FREDERICK ,  KAHLE JAMES ALLAN ,  NGUYENPHU MYHONG ,  RAY DAVID SCOTT

    IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48 ,  G06F9/46

    Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

    TIGHTLY COUPLED MULTIPROCESSOR INSTRUCTION SYNCHRONIZATION
    9.
    发明专利
    TIGHTLY COUPLED MULTIPROCESSOR INSTRUCTION SYNCHRONIZATION 未知

    公开(公告)号：AU618142B2

    公开(公告)日：1991-12-12

    申请号：AU4433789

    申请日：1989-11-02

    Applicant: IBM

    Inventor： GROHOSKI GREGORY FREDERICK ,  RAY DAVID SCOTT ,  NGUYENPHU MYHONG ,  KAHLE JAMES ALLAN

    IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48

    Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

    DATA PROCESSING SYSTEMS
    10.
    发明专利
    DATA PROCESSING SYSTEMS 未知

    公开(公告)号：GB2227108A

    公开(公告)日：1990-07-18

    申请号：GB8928776

    申请日：1989-12-20

    Applicant: IBM

    Inventor： GROHOSKI GREGORY FREDERICK ,  KAHLE JAMES ALLAN ,  NGUYENPHU MYHONG ,  RAY DAVID SCOTT

    IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48

    Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

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