公开(公告)号：BR9000112A

公开(公告)日：1990-10-23

申请号：BR9000112

申请日：1990-01-12

Applicant: IBM

Inventor： GROHOSKI GREGORY FREDERICK ,  KAHLE JAMES ALLAN ,  NGUYENPHU MYHONG ,  RAY DAVID SCOTT

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48 ,  G06F15/80

Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

公开(公告)号：PH30201A

公开(公告)日：1997-02-05

申请号：PH39687

申请日：1989-12-13

Applicant: IBM

Inventor： GROHOSKI GREGORY F ,  KAHLE JAMES A ,  NGUYENPHU MYHONG ,  RAY DAVID S

IPC: G06F9/38 ,  G06F15/16 ,  G06F9/48 ,  G06F1/00

Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

公开(公告)号：AU6675390A

公开(公告)日：1991-06-27

申请号：AU6675390

申请日：1990-11-20

Applicant: IBM

Inventor： HICKS TROY NEAL ,  NGUYENPHU MYHONG

IPC: G06F9/38 ,  G06F15/16 ,  G06F13/12

Abstract: A data processing system having an instruction execution circuit 16 that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type in a queue 30 while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.

公开(公告)号：DE68928015D1

公开(公告)日：1997-06-05

申请号：DE68928015

申请日：1989-12-20

Applicant: IBM

Inventor： NGUYENPHU MYHONG ,  THATCHER LARRY EDWARD

IPC: G06F15/16 ,  G06F9/34 ,  G06F9/38 ,  G06F7/48

Abstract: A data processing system including a first processor that performs fixed point arithmetic operations and a second processor that performs floating point arithmetic operations. These two processors are connected by control circuitry that decodes a floating point arithmetic instruction that requires the second processor to perform a specified floating point arithmetic operation. The control circuitry provides information to the first processor to enable the first processor to compute a memory address for accessing the floating point data required by the second processor for performing the specified floating point arithmetic operation. Simultaneously the control circuitry provides the second processor with the information to initiate the execution of the specified floating point arithmetic operation. Also, the data processing system includes the means to access multi-word floating point data on either even or odd memory address boundaries.

公开(公告)号：DE69017178T2

公开(公告)日：1995-08-10

申请号：DE69017178

申请日：1990-12-07

Applicant: IBM

Inventor： HICKS TROY NEAL ,  NGUYENPHU MYHONG

IPC: G06F9/38 ,  G06F15/16

Abstract: A data processing system having an instruction execution circuit 16 that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type in a queue 30 while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.

公开(公告)号：DE69017178D1

公开(公告)日：1995-03-30

申请号：DE69017178

申请日：1990-12-07

Applicant: IBM

Inventor： HICKS TROY NEAL ,  NGUYENPHU MYHONG

IPC: G06F9/38 ,  G06F15/16

Abstract: A data processing system having an instruction execution circuit 16 that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type in a queue 30 while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.

公开(公告)号：CA1321655C

公开(公告)日：1993-08-24

申请号：CA608713

申请日：1989-08-18

Applicant: IBM

Inventor： GROHOSKI GREGORY F ,  KAHLE JAMES A ,  NGUYENPHU MYHONG ,  RAY DAVID S

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48

Abstract: AT9-88-080 TIGHTLY COUPLED MULTIPROCESSOR INSTRUCTION SYNCHRONIZATION A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

公开(公告)号：DE68927911T2

公开(公告)日：1997-09-18

申请号：DE68927911

申请日：1989-12-20

Applicant: IBM

Inventor： GROHOSKI GREGORY FREDERICK ,  KAHLE JAMES ALLAN ,  NGUYENPHU MYHONG ,  RAY DAVID SCOTT

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48 ,  G06F9/46

Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

公开(公告)号：DE68927911D1

公开(公告)日：1997-04-30

申请号：DE68927911

申请日：1989-12-20

Applicant: IBM

Inventor： GROHOSKI GREGORY FREDERICK ,  KAHLE JAMES ALLAN ,  NGUYENPHU MYHONG ,  RAY DAVID SCOTT

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48 ,  G06F9/46

Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

公开(公告)号：DE68923264T2

公开(公告)日：1996-02-08

申请号：DE68923264

申请日：1989-12-20

Applicant: IBM

Inventor： COCANOUGHER DANIEL ,  MONTOYE ROBERT KEVIN ,  NGUYENPHU MYHONG ,  RUNYON STEPHEN LARRY

IPC: G06F7/38 ,  G06F7/485 ,  G06F7/487 ,  G06F7/527 ,  G06F7/544 ,  G06F7/57 ,  G06F7/48

Abstract: A processor for performing floating point arithmetic operations includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.