公开(公告)号：FI922350A0

公开(公告)日：1992-05-22

申请号：FI922350

申请日：1992-05-22

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASKHAKORI ESMAEIL

IPC: G06F13/36 ,  G06F13/18 ,  G06F13/362 ,  G06F

Abstract: This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.

公开(公告)号：FR2613094B1

公开(公告)日：1990-02-16

申请号：FR8718197

申请日：1987-12-21

Applicant: IBM

Inventor： LO YUAN-CHANG ,  SZAREK JOHN JOSEPH ,  MOELLER DENNIS LEE

IPC: G06F12/16 ,  G06F11/22 ,  G06F12/06 ,  G11C29/00 ,  G06F12/02 ,  G06F11/20

Abstract: A microcomputer system has first, low order address, memory means (17) soldered to the planar printed circuit board and can accept further memory means (18) pluggable into socket means on the board. At power on self test, the memory means are tested, and, if an error is detected in the first memory means, this memory means is disabled by directing the lowest order memory addresses to the second memory means and reducing the highest order addresses by the number of locations in the first memory means.

公开(公告)号：ZA8500183B

公开(公告)日：1985-11-27

申请号：ZA8500183

申请日：1985-01-08

Applicant: IBM

Inventor： DEAN MARK EDWARD ,  MOELLER DENNIS LEE

IPC: G06F13/28 ,  G06F

CPC classification number: G06F13/285

公开(公告)号：AU3409984A

公开(公告)日：1985-07-04

申请号：AU3409984

申请日：1984-10-10

Applicant: IBM

Inventor： DEAN MARK EDWARD ,  MOELLER DENNIS LEE

IPC: G06F9/46 ,  G06F9/38 ,  G06F11/00 ,  G06F11/07 ,  G06F13/36 ,  G06F15/16 ,  G06F15/177

Abstract: In a data processing system including a main processor (1) and a co-processor (2), a logic circuit (6) is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honour the interrupt before executing another co-processor instruction.

公开(公告)号：AT182697T

公开(公告)日：1999-08-15

申请号：AT92304506

申请日：1992-05-19

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F1/24 ,  G06F13/00

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.

公开(公告)号：SG42881A1

公开(公告)日：1997-10-17

申请号：SG1996000404

申请日：1992-05-19

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/18 ,  G06F13/40

Abstract: This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.

公开(公告)号：CA2099026C

公开(公告)日：1996-12-03

申请号：CA2099026

申请日：1993-06-23

Applicant: IBM

Inventor： BLACKLEDGE JOHN WILEY JR ,  DAYAN RICHARD ALAN ,  MOELLER DENNIS LEE ,  NEWMAN PALMER EUGENE ,  ZUBAY KENNETH JOHN PETER

IPC: G06F12/14 ,  G06F1/00 ,  G06F21/02 ,  G06F21/24

Abstract: This invention relates to personal computer systems and, more particularly, to such a system having security features enabling control over access to data retained in such a system. This invention contemplates protecting a personal computer system which has the capability of becoming a secure system from being placed into that condition by an attack on an unsecured machine. Additionally, in a network environment, it is important to maintain network security that any given particular system be uniquely identified to the network, in order to guard against the substitution of an insecure "alternate" which would open the network to attack through an insecure system. This invention contemplates provision for such identification in a secure manner.

公开(公告)号：NZ245756A

公开(公告)日：1995-12-21

申请号：NZ24575693

申请日：1993-01-26

Applicant: IBM

Inventor： BLACKLEDGE JOHN WILEY ,  CLARKE GRANT LEACH ,  DAYAN RICHARD ALAN ,  LE KIMTHANH DO ,  MCCOURT PATRICK EDWARD ,  MITTELSTEDT MATTHEW TODD ,  MOELLER DENNIS LEE ,  NEWMAN PALMER EUGENE ,  RANDALL DAVE LEE ,  YODER JOANNA BERGER

IPC: G06F9/06 ,  G06F12/14 ,  G06F21/00 ,  G06F11/00 ,  G06F21/06 ,  G06F21/22 ,  G06F21/24 ,  G06F1/16

Abstract: This invention relates to personal computer systems and, more particularly, to such a system having security features enabling control over access to data retained in such a system. In particular, a personal computer system in accordance with this invention has a normally closed enclosure, an erasable memory element for selective activation to active and inactive states and for receiving and storing a privileged access password when in the active state, an option switch operatively connected with the erasable memory element for setting the erasable memory element to the active and inactive states, a tamper detection switch operatively connected with the erasable memory element for detecting opening of the enclosure and for clearing any stored privileged access password from the erasable memory element in response to any switching of the tamper switch, and a system processor operatively connected with the erasable memory element for controlling access to at least certain levels of data stored within the system by distinguishing between the active and inactive states of the memory element and between entry and non-entry of any stored privileged access password. In the presently preferred form of the invention, two non-volatile erasable memory elements are provided, one an EEPROM and the other battery backed CMOS RAM.

公开(公告)号：AU663551B2

公开(公告)日：1995-10-12

申请号：AU3201993

申请日：1993-01-25

Applicant: IBM

Inventor： BLACKLEDGE JOHN WILEY JR ,  CLARKE GRANT LEACH JR ,  DAYAN RICHARD ALAN ,  LE KIMTHANH DO ,  MCCOURT PATRICK EDWARD ,  MITTELSTEDT MATTHEW TODD ,  MOELLER DENNIS LEE ,  NEWMAN PALMER EUGENE ,  RANDALL DAVE LEE ,  YODER JOANNA BERGER

IPC: G06F11/00 ,  G06F9/06 ,  G06F12/14 ,  G06F21/00 ,  G06F21/06 ,  G06F21/22 ,  G06F21/24

Abstract: This invention relates to personal computer systems and, more particularly, to such a system having security features enabling control over access to data retained in such a system. In particular, a personal computer system in accordance with this invention has a normally closed enclosure, an erasable memory element for selective activation to active and inactive states and for receiving and storing a privileged access password when in the active state, an option switch operatively connected with the erasable memory element for setting the erasable memory element to the active and inactive states, a tamper detection switch operatively connected with the erasable memory element for detecting opening of the enclosure and for clearing any stored privileged access password from the erasable memory element in response to any switching of the tamper switch, and a system processor operatively connected with the erasable memory element for controlling access to at least certain levels of data stored within the system by distinguishing between the active and inactive states of the memory element and between entry and non-entry of any stored privileged access password. In the presently preferred form of the invention, two non-volatile erasable memory elements are provided, one an EEPROM and the other battery backed CMOS RAM.

公开(公告)号：NO922092A

公开(公告)日：1992-11-30

申请号：NO922092

申请日：1992-05-26

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/362 ,  G06F13/40 ,  G06F13/20

CPC classification number: G06F13/362 ,  G06F13/4031