公开(公告)号：IE990422A1

公开(公告)日：2000-03-22

申请号：IE990422

申请日：1999-05-25

Applicant: IBM

Inventor： NEAL DANNY MARVIN ,  THURBER STEVEN MARK ,  BEUKEMA BRUCE LEROY ,  FUHS RONALD EDWARD ,  KELLEY RICHARD ALLEN

IPC: G06F13/40 ,  G06F13/368

Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions or alias split transactions to delayed transactions. Backward compatibility may also be provided for optional features such as hot-pluggability.

公开(公告)号：PL333006A1

公开(公告)日：1999-11-08

申请号：PL33300697

申请日：1997-09-30

Applicant: IBM

Inventor： GUTHRIE GUY LYNN ,  NEAL DANNY MARVIN ,  KELLEY RICHARD ALLEN

IPC: G06F13/40

Abstract: A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter, residing within a Host Bridge, Control & Power logic, and a plurality of in-line switch modules coupled to a bus. Each of the in-line switch modules provide isolation for load(s) connected thereto. The Host Bridge in combination with the Control & Power Logic implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).

公开(公告)号：GB2334120A

公开(公告)日：1999-08-11

申请号：GB9909356

申请日：1997-09-30

Applicant: IBM

Inventor： GUTHRIE GUY LYNN ,  NEAL DANNY MARVIN ,  KELLEY RICHARD ALLEN

IPC: G06F13/40 ,  G06F1/00

Abstract: A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter (202a), residing within a Host Bridge (202), Control and Power Logic (208), and a plurality of in-line switch modules (326, 328) coupled to a bus. Each of the in-line switch modules (326, 328) provides isolation for load(s) connected thereto. The Host Bridge (202) in combination with the Control and Power Logic (208) implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).

公开(公告)号：CA2236060A1

公开(公告)日：1998-12-11

申请号：CA2236060

申请日：1998-04-28

Applicant: IBM

Inventor： NEAL DANNY MARVIN ,  THURBER STEVEN MARK ,  CLOUSER PAUL L ,  JOHNS CHARLES RAY ,  KELLEY RICHARD ALLEN

IPC: G06F13/00 ,  G06F13/368 ,  G06F13/38

Abstract: A peripheral component interconnect (PCI) bus is adapted for differential signal ling. Two signal lines are providing for each bus signal and information is encoded as either a polarity or a magnitude of a voltage difference between the two signal lines. En hanced PCI compliant devices include drivers and receivers capable of differential sign alling. The resulting bus architecture supports clocking data on both edges as well as sourc e synchronous clocking. The enhanced PCI bus architecture also supports data block ing, pacing, split transactions, and synchronization commands.

公开(公告)号：CH647198A5

公开(公告)日：1985-01-15

申请号：CH351779

申请日：1979-04-12

Applicant: IBM

Inventor： CLANCY DOUGLAS EUGENE ,  JOHNSON CARL FOSTER ,  MCCRAY WILLIAM ROY ,  NEAL DANNY MARVIN

IPC: B41J19/18 ,  B41J21/08 ,  B41J21/17 ,  B41J29/36 ,  G06F17/24 ,  B41J19/60

公开(公告)号：CH644063A5

公开(公告)日：1984-07-13

申请号：CH289979

申请日：1979-03-29

Applicant: IBM

Inventor： BOWLES DAVID JOHN ,  CLANCY DOUGLAS EUGENE ,  JOHNSON CARL FOSTER ,  NEAL DANNY MARVIN

IPC: B41J19/64 ,  B41J21/00 ,  B41J29/26 ,  B41J29/36

公开(公告)号：AU4597479A

公开(公告)日：1979-11-29

申请号：AU4597479

申请日：1979-04-12

Applicant: IBM

Inventor： BOWLES DAVID JOHN ,  CLANCY DOUGLAS EUGENE ,  JOHNSON CARL FOSTER ,  NEAL DANNY MARVIN

IPC: B41J29/18 ,  B41J21/17 ,  B41J25/04 ,  B41J29/36 ,  B41J29/42 ,  B41J19/58 ,  B41J19/50

Abstract: On electronic typewriters which have the ability to record into a small working memory those characters, functions and escapements which are keyed at the keyboard, it is many times advantageous to be able to place the carrier and the print point over a character which has been previously typed without using repeated backspaces. Disclosed herein is a feature for an electronic typewriter which permits the operator to easily align the print point with a character on the page by positioning a reference mark on the card holder or print carrier in relation to a previously printed character and then through keyboard control cause the carriage to shift its position such that the print point is then exactly aligned with the character printed. The positioning of the carrier such that the reference mark is in relation to the desired print point is accomplished by a backspace operation and the repositioning or causing of the carrier to assume a position immediately over the subject character is accomplished by keyboard control through the electronics of the typewriter to cause the carrier to shift a predetermined distance.