公开(公告)号：JP2002198538A

公开(公告)日：2002-07-12

申请号：JP2001319845

申请日：2001-10-17

Applicant: IBM

Inventor： ADKISSON JAMES W ,  AGNELLO PAUL D ,  ARNE W BALLANTINE ,  DIVAKARUNI RAMA ,  JONES ERIN C ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L29/161 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a dual-gate transistor having a relatively thin epitaxial growth channel. SOLUTION: The epitaxial growth channel is formed, and then a damascene gate is formed, thus forming a silicon-on-insulator(SOI) MOSFET of a dual gate. In the dual-gate MOSFET, a narrow channel should be provided, thus increasing a current drive per layout width, and achieving low out conductance.

公开(公告)号：JPH11260936A

公开(公告)日：1999-09-24

申请号：JP1651299

申请日：1999-01-26

Applicant: IBM

Inventor： NOWAK EDWARD J ,  MIN HOO TON

IPC: H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a series of field-effect transistors(FETs), each of which has the gate oxide layer of a single thickness on a silicon wafer but is driven by different operating voltage. SOLUTION: A plysilicon gate layer is formed on a gate dielectric layer (oxide) 138 on a silicon wafer. During the period when an ordinary NFET 120 and a PFET 124 are formed, the determined position of a high-voltage FET is shielded. After the formation of the ordinary FET, the shield of the high-voltage FET is removed. Recommendably, the dopant of boron (B) or phosphorus (P) is injected into a gate and a source/drain region with a specified concentration and a specified energy. As a result, the gate and the source/drain region is depleted. An effective gate dielectric layer 136, which is thicker than the ordinary NFET 120 and PFET 124, is obtained.

公开(公告)号：WO2012054144A3

公开(公告)日：2012-08-16

申请号：PCT/US2011050502

申请日：2011-09-06

Applicant: IBM ,  ANDERSON BRENT A ,  NOWAK EDWARD J

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/26586 ,  H01L29/66803 ,  H01L29/785

Abstract: FinFET end-implanted-semiconductor structures and methods of manufacture are disclosed herein. The method includes forming at least one mandrel (14 in Fig. 5) on a silicon layer of a substrate (18') comprising an underlying insulator layer (10b). The method further includes etching the silicon layer to form at least one silicon island (18') under the at least one mandrel. The method further comprises ion- implanting sidewalls of the at least one silicon island to form doped regions (20) on the sidewalls. The method further includes forming a dielectric layer on the substrate, a top surface of which is planarized to be coplanar with a top surface of the at least one mandrel (14). The method further includes removing the at least one mandrel (14) to form an opening in the dielectric layer. The method further comprises etching the at least one silicon island to form at least one fin island having doped source and drain regions.

Abstract translation: FinFET端部注入半导体结构和制造方法在本文中公开。 该方法包括在包括下面的绝缘体层（10b）的衬底（18'）的硅层上形成至少一个心轴（图5中的14）。 该方法还包括蚀刻硅层以在至少一个心轴下形成至少一个硅岛（18'）。 该方法还包括离子注入至少一个硅岛的侧壁，以在侧壁上形成掺杂区域（20）。 该方法还包括在基底上形成介电层，其顶表面被平坦化以与至少一个心轴（14）的顶表面共平面。 该方法还包括去除至少一个心轴（14）以在电介质层中形成开口。 该方法还包括蚀刻至少一个硅岛以形成具有掺杂源极和漏极区域的至少一个鳍岛。

公开(公告)号：WO2008106574A3

公开(公告)日：2009-01-29

申请号：PCT/US2008055214

申请日：2008-02-28

Applicant: IBM ,  ANDERSON BRENT A ,  NOWAK EDWARD J ,  SCHONENBERG KATHRYN T

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  SCHONENBERG KATHRYN T

IPC: H01L29/49

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A structure and a method for forming the same. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin region. The gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region. The structure further includes a first spacer region on a first side wall of the gate electrode region. A first side wall of the semiconductor fin region is exposed to a surrounding ambient. A top surface of the first spacer region is coplanar with a top surface of the gate electrode region.

Abstract translation: 一种结构及其形成方法。 该结构包括（a）衬底，（b）在衬底的顶部上的半导体鳍片区域，（c）半导体鳍片区域的侧壁上的栅极电介质区域，以及（d）顶部和上部的栅电极区域 半导体鳍片区域的侧壁。 栅极电介质区域（i）夹在其间并且（ii）使栅电极区域和半导体鳍片区域电绝缘。 该结构还包括在栅电极区域的第一侧壁上的第一间隔区域。 半导体鳍片区域的第一侧壁暴露于周围环境。 第一间隔区域的顶表面与栅电极区域的顶表面共面。

公开(公告)号：WO2004100290A3

公开(公告)日：2005-02-24

申请号：PCT/US2004002647

申请日：2004-01-30

Applicant: IBM ,  RAINEY BETH ANN ,  NOWAK EDWARD J ,  ALLER INGO DR ,  KEINERT JOACHIM ,  LUDWIG THOMAS

Inventor： RAINEY BETH ANN ,  NOWAK EDWARD J ,  ALLER INGO DR ,  KEINERT JOACHIM ,  LUDWIG THOMAS

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/772

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66795

Abstract: The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.

Abstract translation: 本发明提供一种具有第一鳍片和第二鳍片的FinFET器件。 每个散热片具有从沟道区延伸的沟道区和源极和漏极区。 翅片具有不同的高度。 本发明具有邻近散热片定位的栅极导体。 栅极导体垂直于翅片延伸并与第一鳍片和第二鳍片中的每一个的沟道区域交叉。 翅片彼此平行。 第一翅片的高度与第二翅片的高度的比率为1/2/3的比例。 该比率用于调整晶体管的性能并确定晶体管的总通道宽度。

公开(公告)号：WO2010151400A3

公开(公告)日：2011-02-24

申请号：PCT/US2010036980

申请日：2010-06-02

Applicant: IBM ,  ANDERSON BRENT A ,  NOWAK EDWARD J

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L21/28123 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785

Abstract: A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates (16 of FIG. 6) about a plurality of active regions and depositing a dielectric material (18a and in space 20) over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions of the dielectric material (20) to expose the temporary spacer gates (16) and removing the temporary spacer gates, leaving a space between the active regions and a remaining portion of the dielectric material (18a). The method additionally includes filling the space (20) between the active regions and above the remaining portion of the dielectric material (18a) with a gate material.

Abstract translation: 显示了MUGFET和制造MUGFET的方法。 制造MUGFET的方法包括：围绕多个有源区形成临时隔离栅（图6中的16），并在包括多个有源区之间的临时间隔栅上沉积电介质材料（18a和空间20）。 该方法还包括蚀刻电介质材料（20）的部分以暴露临时隔离栅极（16）并移除临时隔离栅极，在有源区域和电介质材料（18a）的剩余部分之间留下空间。 该方法还包括用栅极材料填充有源区域之间的空间（20）和电介质材料（18a）的剩余部分之上。

公开(公告)号：WO2008033982A2

公开(公告)日：2008-03-20

申请号：PCT/US2007078366

申请日：2007-09-13

Applicant: IBM ,  ANDERSON BRENT A ,  LUDWIG THOMAS ,  NOWAK EDWARD J

Inventor： ANDERSON BRENT A ,  LUDWIG THOMAS ,  NOWAK EDWARD J

IPC: H01L29/76

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66613 ,  H01L29/66795 ,  H01L2029/7858

Abstract: Therefore, disclosed above are embodiments of a multi-fin field effect transistor structure (300 or 400) (e.g., a multi-fin dual-gate FET or tri-gate FET) that provides low resistance strapping of the source/drain regions (41, 42) of the fins (60a-c), while also maintaining low capacitance to the gate (80) by raising the level of the straps (71, 72) above the level of the gate (80). Embodiments of the structure of the invention incorporate either conductive vias (31, 32) (see structure 300) or taller source/drain regions (see structure 400) in order to electrically connect the source/drain straps (71, 72) to the source/drain regions (41, 42) of each fin (60a-c). Also, disclosed are embodiments of associated methods of forming these structures.

Abstract translation: 因此，上面公开的是提供源极/漏极区域（41）的低电阻贴片的多鳍场效应晶体管结构（300或400）（例如，多鳍双栅极FET或三栅极FET）的实施例 ，42）的翅片（60a-c），同时通过将带（71,72）的电平提高到门（80）的高度以上，同时保持对门（80）的低电容。 本发明的结构的实施例包括导电通孔（31,32）（见结构300）或更高的源极/漏极区域（参见结构400），以将源极/漏极带（71,72）电连接到源极 /漏区（41,42）。 此外，公开了形成这些结构的相关方法的实施例。

公开(公告)号：WO2006044349A3

公开(公告)日：2007-06-07

申请号：PCT/US2005036471

申请日：2005-10-11

Applicant: IBM ,  ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L29/04 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A planar substrate device (100) integrated with fin field effect transistors (FinFETs) and a method of manufâcture comprises a silicon-on-insulator (SOI) wafer (101) comprising a substrate (103); a buried insulator layer (105) over the substrate (103); and a semiconductor layer (115) over the buried insulator layer (105). The structure (100) further comprises a FinFET (130) over the buried insulator layer (105) and a field effect transistor (FET) (131) integrated in the substrate (103), wherein the FET (127) gate is planar to the FinFET gate (125). The structure (100) further comprises retrograde well regions (104, 106, 108, 110) configured in the substrate (103). In one embodiment, the structure (100) further comprises a shallow trench isolation region (111) configured in the substrate (103).

Abstract translation: 与鳍状场效应晶体管（FinFET）集成的平面基板装置（100）和制造方法包括：包含基板（103）的绝缘体上硅（SOI）晶片（101）; 在所述衬底（103）上方的掩埋绝缘体层（105）; 以及在所述掩埋绝缘体层（105）上方的半导体层（115）。 所述结构（100）还包括在所述掩埋绝缘体层（105）上的FinFET（130）和集成在所述衬底（103）中的场效应晶体管（FET）（131），其中所述FET（127）栅极与 FinFET门（125）。 结构（100）还包括配置在基底（103）中的逆行井区（104,106,108,110）。 在一个实施例中，结构（100）还包括构造在衬底（103）中的浅沟槽隔离区（111）。

公开(公告)号：WO2005001905A3

公开(公告)日：2006-02-23

申请号：PCT/US2004020553

申请日：2004-06-25

Applicant: IBM ,  NOWAK EDWARD J

Inventor： NOWAK EDWARD J

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: The invention provides a method of manufacturing a fin-type field effect transistor (FinFET) that begins by patterning a rectangular loop of semiconductor material (16) having two longer fins (21) and two shorter sections (22). The longer fins (21) are perpendicular to the shorter sections (22). The process continues by patterning a rectangular gate conductor (20) over central sections of the two longer fins (21), wherein the gate conductor (20) is perpendicular to the two longer fins (21). Next, the invention dopes portions of the semiconductor material (11) not covered by the gate conductor (20) to form source and drain regions in portions of the fins (21) that extend beyond the gate (20). Following this, the invention forms insulating sidewalls (31) along the gate conductor (20). Then, the invention covers the gate conductor (20) and the semiconductor material (11) with a conductive contact material (30) and forms a contact mask (40) over a portion of the conductive contact material (30) that is above source and drain regions of a first fin (42) of the two longer fins (21). The invention follows this by selectively etching regions of the conductive contact material (30) and the semiconductor material (11) not protected by the contact mask. This leaves the conductive contact material (30) on source and drain regions of the first fin (42) and removes source and drain regions of a second fin (41) of the two longer fins (21). This process forms a unique FinFET that has a first fin (42) with a central channel region (55) and source and drain regions (56) adjacent the channel region (55), a gate (20) intersecting the first fin (42) and covering the channel region (55), and a second fin (41) having only a channel region. The second fin is parallel to the first fin (42) and covered by the gate.

Abstract translation: 本发明提供一种制造翅片型场效应晶体管（FinFET）的方法，其通过图案化具有两个较长翅片（21）和两个较短部分（22）的半导体材料（16）的矩形环开始。 较长的翅片（21）垂直于较短的部分（22）。 该过程继续通过在两个较长翅片（21）的中心部分上形成矩形栅极导体（20），其中栅极导体（20）垂直于两个较长的翅片（21）。 接下来，本发明掺杂未被栅极导体（20）覆盖的半导体材料（11）的部分，以在散热片（21）的延伸超过栅极（20）的部分中形成源区和漏极区。 之后，本发明沿着栅极导体（20）形成绝缘侧壁（31）。 然后，本发明用导电接触材料（30）覆盖栅极导体（20）和半导体材料（11），并在导电接触材料（30）的高于源极的部分上形成接触掩模（40），并且 两个较长翅片（21）的第一翅片（42）的漏极区域。 本发明通过选择性地蚀刻导电接触材料（30）的区域和未被接触掩模保护的半导体材料（11）来实现。 这使得导电接触材料（30）在第一鳍片（42）的源极和漏极区域上离开，并且去除两个较长翅片（21）的第二鳍片（41）的源极和漏极区域。 该过程形成独特的FinFET，其具有带有中心沟道区域（55）的第一鳍片（42）和与沟道区域（55）相邻的源极和漏极区域（56），与第一鳍片（42）相交的栅极（20） 并且覆盖沟道区域（55）和仅具有沟道区域的第二鳍片（41）。 第二鳍片平行于第一鳍片（42）并被栅极覆盖。

公开(公告)号：WO2007015957A3

公开(公告)日：2007-12-06

申请号：PCT/US2006028312

申请日：2006-07-21

Applicant: IBM ,  ANDERSON BRENT A ,  BREITWISCH MATTHEW J ,  NOWAK EDWARD J ,  RAINEY BETHANN

Inventor： ANDERSON BRENT A ,  BREITWISCH MATTHEW J ,  NOWAK EDWARD J ,  RAINEY BETHANN

IPC: H01L29/12 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78615 ,  H01L29/78687

Abstract: A field effect transistor (FET) and method of forming the FET comprises a substrate (101 ); a silicon germanium (SiGe) layer (103) over the substrate (103); a semiconductor layer (105) over and adjacent to the SiGe layer (103); an insulating layer (109a) adjacent to the substrate (101), the SiGe layer (103), and the semiconductor layer (105); a pair of first gate structures (111) adjacent to the insulating layer (1 09a); and a second gate structure (113) over the insulating layer (109a). Preferably, the insulating layer (109a) is adjacent to a side surface of the SiGe layer (103) and an upper surface of the semiconductor layer (105), a lower surface of the semiconductor layer (105), and a side surface of the semiconductor layer (105). Preferably, the SiGe layer (103) comprises carbon. Preferably, the pair of first gate structures (111) are substantially transverse to the second gate structure (113). Additionally, the pair of first gate structures (111) are preferably encapsulated by the insulating layer (109a).

Abstract translation: 场效应晶体管（FET）和形成FET的方法包括：衬底（101）; 在所述衬底（103）上方的硅锗（SiGe）层（103）; 在所述SiGe层（103）上并邻近所述半导体层（105）; 与基板（101）相邻的绝缘层（109a），SiGe层（103）和半导体层（105）; 与绝缘层（109a）相邻的一对第一栅极结构（111）; 和绝缘层（109a）上的第二栅极结构（113）。 优选地，绝缘层（109a）与SiGe层（103）的侧表面和半导体层（105）的上表面，半导体层（105）的下表面和 半导体层（105）。 优选地，SiGe层（103）包含碳。 优选地，一对第一栅极结构（111）基本上横向于第二栅极结构（113）。 另外，一对第一栅极结构（111）优选地被绝缘层（109a）封装。