公开(公告)号：JP2002198538A

公开(公告)日：2002-07-12

申请号：JP2001319845

申请日：2001-10-17

Applicant: IBM

Inventor： ADKISSON JAMES W ,  AGNELLO PAUL D ,  ARNE W BALLANTINE ,  DIVAKARUNI RAMA ,  JONES ERIN C ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L29/161 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a dual-gate transistor having a relatively thin epitaxial growth channel. SOLUTION: The epitaxial growth channel is formed, and then a damascene gate is formed, thus forming a silicon-on-insulator(SOI) MOSFET of a dual gate. In the dual-gate MOSFET, a narrow channel should be provided, thus increasing a current drive per layout width, and achieving low out conductance.

公开(公告)号：JP2000228405A

公开(公告)日：2000-08-15

申请号：JP2000023868

申请日：2000-02-01

Applicant: IBM

Inventor： ARNE W BALLANTINE ,  DOUGLAS D KUURUBOU ,  JEFFREY GILBERT ,  JOSEPH R GRECO ,  GLENN R MILLER

IPC: H01L29/73 ,  H01L21/314 ,  H01L21/318 ,  H01L21/328 ,  H01L21/331 ,  H01L29/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming, at least, one interface region between two semiconductor material regions. SOLUTION: Dielectric regions 9 are partially formed at an interface 5 between a single crystal silicon 1 and a polycrystalline silicon 3. The dielectric regions 9 are formed by injecting nitrogen atoms into the single crystal silicon 1. The formed dielectric regions 9 have thickness of 1 to 10 Å. A dielectric layer is provided at an interface between two silicons by the use of nitrogen, by which each wafer can be controlled in electric resistance at an interface. In an NPN transistor, a dielectric layer is formed between an emitter and a contact, by which a base current and a current gain β can be controlled.

公开(公告)号：MY126811A

公开(公告)日：2006-10-31

申请号：MYPI20011417

申请日：2001-03-27

Applicant: IBM

Inventor： JOHN J ELLIS-MONAGHAN ,  TOSHIHARU FURUKAWA ,  ARNE W BALLANTINE ,  GLENN R MILLER ,  JAMES A SLINKMAN ,  JEFFREY D GILBERT

IPC: H01L21/04 ,  H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324 ,  H01L21/326

Abstract: A METHOD FOR FORMING A DESIRED JUNCTION PROFILE IN A SEMICONDUCTOR DEVICE . AT LEAST DOPANT IS INTRODUCED INTO A SEMICONDUCTOR SUBSRATE. THE AT LEAST ONE DOPANT IS DIFFUSED IN THE SEMICONDUCTOR SUBSTRATE THROUGH ANNEALING THE SEMICONDUCTOR SUBSTRATE AND THE AT LEAST ONE DOPANT WHILE SIMULTANEOUSLY EXPOSING THE SEMICONDUCTOR SUBSTRATE TO AN ELECTIC FIELD. (FIG. 5)

公开(公告)号：SG101499A1

公开(公告)日：2004-01-30

申请号：SG200106666

申请日：2001-10-29

Applicant: IBM

Inventor： ANTHONY K STAMPER ,  ARNE W BALLANTINE ,  DANIEL CHARLES EDELSTEIN

IPC: H01C17/06 ,  H01C7/00 ,  H01C17/26 ,  H01L27/08 ,  H01L29/8605

Abstract: A method for increasing an electrical resistance of a resistor that is within a semiconductor structure. A fraction of a surface layer of the resistor is oxidized with oxygen particles. In an embodiment, the fraction of the surface layer is heated by a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen particles as gaseous oxygen-comprising molecules. In an embodiment, the semiconductor structure is immersed in a chemical solution which includes the oxygen particles, wherein the oxygen particles includes oxygen-comprising liquid molecules, oxygen ions, or an oxygen-comprising gas dissolved in the chemical solution under pressurization. In an embodiment, the resistor is tested to determine whether the electrical resistance of the resistor after being oxidized with the oxygen particles is within a tolerance of a predetermined target resistance.

公开(公告)号：SG100658A1

公开(公告)日：2003-12-26

申请号：SG200101933

申请日：2001-03-26

Applicant: IBM

Inventor： ARNE W BALLANTINE ,  JOHN J ELLIS-MONAGHAN ,  TOSHIHARU FURUKAWA ,  GLENN R MILLER ,  JAMES ALBERT SLINKMAN ,  JEFFERY D GILBERT

IPC: H01L21/22 ,  C21D1/04 ,  H01L21/225 ,  H01L21/26 ,  H01L21/265 ,  H01L21/324 ,  H01L21/326 ,  H01L21/00

Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

公开(公告)号：SG97204A1

公开(公告)日：2003-07-18

申请号：SG200106328

申请日：2001-10-12

Applicant: IBM

Inventor： JAMES W ADKISSON ,  PAUL D AGNELLO ,  ARNE W BALLANTINE ,  RAMA DIVAKARUNI ,  ERIN JONES ,  EDWARD JOSEPH NOWAK ,  JED H RANKIN

IPC: H01L29/161 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：SG96265A1

公开(公告)日：2003-05-23

申请号：SG200107623

申请日：2001-12-06

Applicant: IBM

Inventor： ARNE W BALLANTINE ,  JEFFREY SCOTT BROWN ,  JEFFREY D GILBERT ,  JAMES J QUINLIVAN ,  JAMES ALBERT SLINKMAN ,  ANTHONY C SPERANZA

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L21/31

Abstract: A structure comprising a trench having a liner with rounded corners in the top and bottom of the trench is obtained by rapid thermal oxidation.