公开(公告)号：EP1665334A4

公开(公告)日：2011-02-23

申请号：EP04756338

申请日：2004-06-29

Applicant: IBM

Inventor： PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/425 ,  H01L21/4763 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78621

公开(公告)号：JP2002198538A

公开(公告)日：2002-07-12

申请号：JP2001319845

申请日：2001-10-17

Applicant: IBM

Inventor： ADKISSON JAMES W ,  AGNELLO PAUL D ,  ARNE W BALLANTINE ,  DIVAKARUNI RAMA ,  JONES ERIN C ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L29/161 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a dual-gate transistor having a relatively thin epitaxial growth channel. SOLUTION: The epitaxial growth channel is formed, and then a damascene gate is formed, thus forming a silicon-on-insulator(SOI) MOSFET of a dual gate. In the dual-gate MOSFET, a narrow channel should be provided, thus increasing a current drive per layout width, and achieving low out conductance.

公开(公告)号：JP2002324903A

公开(公告)日：2002-11-08

申请号：JP2002068920

申请日：2002-03-13

Applicant: IBM

Inventor： KHARE MUKESH ,  AGNELLO PAUL D ,  CHOU ANTHONY I ,  HOOK TERENCE B ,  MOCUTA ANDA C

IPC: H01L21/74 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method and circuit configuration effective for reducing plasma-induced charging damage on a device fabricated on a silicon-on- insulator(SOI) substrate. SOLUTION: An SOI circuit configuration effective for minimizing plasma- induced charging damage during fabrication comprises formation of charge collectors connected to the gate electrode and a semiconductor body, wherein each of the charge collectors has the same or substantially the same shape and dimension. The formation of a connecting structure between a device formed on the SOI substrate and the substrate is delayed until the later stages of processing.

公开(公告)号：WO2005024899A3

公开(公告)日：2008-11-20

申请号：PCT/US2004020850

申请日：2004-06-29

Applicant: IBM ,  PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

Inventor： PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/425 ,  H01L21/4763 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78621

Abstract: Disclosed is a method and system of forming an integrated circuit transistor having a reduced gate height. The method forms a laminated structure having a substrate, a gate conductor (13) above the substrate, and at least one sacrificial layer (14-16) above the gate conductor (13). The process patterns the laminated structure into at least one gate stack extending from the substrate, forms spacers (60) adjacent to the gate stack, dopes regions of the substrate not protected by the spacers to form source and drain regions (71) adjacent the gate stack, and removes the spacers (60) and the sacrificial layer (14-16).

Abstract translation: 公开了一种形成栅极高度降低的集成电路晶体管的方法和系统。 该方法形成具有衬底，在衬底上方的栅极导体（13）和栅极导体（13）上方的至少一个牺牲层（14-16）的叠层结构。 该过程将层叠结构图案化为从衬底延伸的至少一个栅极堆叠，与栅极叠层相邻形成间隔物（60），不会由间隔物掺杂衬底的区域，以形成邻近栅极的源区和漏区（71） 并且移除间隔物（60）和牺牲层（14-16）。

公开(公告)号：DE60138000D1

公开(公告)日：2009-04-30

申请号：DE60138000

申请日：2001-10-15

Applicant: IBM

Inventor： ADKISSON JAMES W ,  AGNELLO PAUL D ,  BALLANTINE ARNE W ,  DIVAKARUNI RAMA ,  JONES ERIN C ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/336 ,  H01L29/161 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：AT426246T

公开(公告)日：2009-04-15

申请号：AT01308767

申请日：2001-10-15

Applicant: IBM

Inventor： ADKISSON JAMES W ,  AGNELLO PAUL D ,  BALLANTINE ARNE W ,  DIVAKARUNI RAMA ,  JONES ERIN C ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/336 ,  H01L29/161 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：DE102004016700A1

公开(公告)日：2004-11-18

申请号：DE102004016700

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DEHAVEN PATRICK W ,  AGNELLO PAUL D ,  WONG KEITH KWONG HON ,  HUANG HSIANG-JEN ,  MURPHY RICHARD J ,  DZIOBKOWSKI CHET ,  CLEVENGER LAWRENCE ,  LAVOIE CHRISTIAN ,  ROVEDO NIVO ,  FANG SUNFEI

IPC: H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.