公开(公告)号：JP2005197743A

公开(公告)日：2005-07-21

申请号：JP2005000921

申请日：2005-01-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CASEY JON A ,  FERRANTE WILLIAM J ,  KIEWRA EDWARD W ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/28 ,  G01K7/22 ,  H01C7/00 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04

CPC classification number: H01L21/76895 ,  G01K7/226 ,  H01C7/006 ,  H01L21/76224 ,  H01L21/76838

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for forming a thermistor.
SOLUTION: An isolation region is formed in a substrate including at least an upper side layer of a single crystal semiconductor. A salicide precursor layer is formed on the isolation region and the upper side layer. Then, reaction of the salicide precursor and the upper side layer is performed and a salicide which is self-aligned to the upper side layer is formed. Finally, no reaction portion of the salicide precursor is removed, while preserving the portion of the salicide precursor on the isolation region as the main body of the thermistor. In alternative method, an integrated circuit thermistor is formed from a thermistor material region in an embossed region of interlayer dielectric (ILD).
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于形成热敏电阻的结构和方法。 解决方案：在至少包含单晶半导体的上侧层的衬底中形成隔离区。 在隔离区域和上侧层上形成自对准硅化物前体层。 然后，进行自对准硅化物前体与上侧层的反应，形成与上侧层自对准的自对准硅化物。 最后，除去自杀化合物前体的反应部分，同时保留作为热敏电阻的主体的隔离区上的部分自杀化合物前体。 在替代方法中，集成电路热敏电阻由层间电介质（ILD）的压花区域中的热敏电阻材料区域形成。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004214627A

公开(公告)日：2004-07-29

申请号：JP2003396333

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  DOKUMACI OMER H ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/28114 ,  H01L21/26586 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/665

Abstract: PROBLEM TO BE SOLVED: To provide an FET device in which the gate activity, line resistance and S/D extension resistance are improved. SOLUTION: A method for manufacturing a semiconductor transistor device is provided with following steps: a semiconductor substrate is formed; the semiconductor substrate has a gate dielectric layer on its surface; lower gate electrode structure is formed on the surface of the gate dielectric layer and the lower gate electrode structure has a low gate upper surface; a planarized layer is formed on the gate dielectric layer so that the upper part of the lower gate electrode structure is left in an exposed state; upper gate structure is formed on the lower gate electrode structure to form a T-type gate electrode; the lower surface of the upper gate structure and the vertical sidewall of the gate electrode are exposed; the planarized layer is removed; a source/drain extension is formed in the substrate protected from a short channel effect; a sidewall spacer is formed adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewall of the T-type gate electrode. A source/drain region is formed in the substrate. A silicide layer is formed on the upper part of the T-type gate electrode and the upper part of the source/drain region. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2002026148A

公开(公告)日：2002-01-25

申请号：JP2001189096

申请日：2001-06-22

Applicant: IBM

Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  GRUENING ULRIKE ,  SUDO AKIRA

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a new deep trench(DT) collar process which reduces disturbance of strap diffusion to an array metal oxide semiconductor field effect transistor(MOSFET) of a semiconductor device. SOLUTION: By this method, an oxidation barrier layer is formed on a sidewall of the DT provided in the semiconductor substrate, a photoresist layer of specific depth is provided in the trench to remove the oxidation barrier layer to specific depth and expose the trench sidewall, and the remaining photoresist is removed. A layer of a silicon material is stuck on the exposed trench sidewall, and a dielectric layer is formed on the silicon material layer to form a collar. The remaining oxidation barrier layer is removed from the trench and polysilicon which forms a storage node is charged. Consequently, the distance between a MOSFET gate and a DT storage capacitor is maximized, and the effective edge bias of the DT at its peak is reducible without spoiling the storage capacity.

公开(公告)号：JP2001223271A

公开(公告)日：2001-08-17

申请号：JP2001002760

申请日：2001-01-10

Applicant: IBM

Inventor： DIVAKARUNI RAMA ,  NESBIT LARRY A ,  RADENS CARL J

IPC: H01L23/522 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To simultaneously form a line interconnection of a bit line or the like and borderless contact to a diffused part such as bit line contact. SOLUTION: A semiconductor substrate contains a previously patterned gate stack 12 on the substrate, is covered with a first dielectric substance 40 for forming a first level 42 and then deposited with a second dielectric substance 44 to form a second level 46. A line interconnection opening 62 is formed at a second level 46 by a lithography and etching. The etching is continued to a microcrystallized region of an array region 30 of the substrate, and formed with a borderless contact opening between the gate stacks 12 corresponding to the line interconnection such as an opening of the bit line or the like. These openings are filled with one or more conductors to form the contact with the diffused part such as bit line contact or the like corresponding to the line interconnection of the bit line or the like.

公开(公告)号：JP2000164697A

公开(公告)日：2000-06-16

申请号：JP33676599

申请日：1999-11-26

Applicant: IBM ,  SIEMENS AG

Inventor： GARY B BRONER ,  COSTRINI GREG ,  RADENS CARL J ,  RAYNER E SCHNABEL

IPC: H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To achieve low capacitance and low resistance by simultaneously performing the pattern formation of a via and a grooved line in an interlayer dielectric, by simultaneously etching the via and the grooved line, and by simultaneously filling the via and the grooved line with metal. SOLUTION: On a substrate, desired linear features and vertical interconnection are formed (S700). A grooved line and a via are simultaneously etched (S701). A metallization layer is subjected pattern formation by lithography, and is etched by RIE or the like (S702). The via and the grooved line are filled by the same metallization process (S703). The filled via and the grooved line are finished by one-time common etching or polishing process so that a structure has a flat and uniform upper surface (S704). As a result, both of low-capacitance and low-resistance metallization can be formed.

公开(公告)号：JP2000058779A

公开(公告)日：2000-02-25

申请号：JP21476499

申请日：1999-07-29

Applicant: IBM ,  SIEMENS AG

Inventor： BRONNER GARY B ,  ECONOMIKOS LAERTIS ,  JAMMY RAJARAO ,  PARK BYEONGJU ,  RADENS CARL J ,  SCHREMS MARTIN E

IPC: H01L21/02 ,  H01L21/3215 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To provide a trench capacitor structure suited for use in a semiconductor integrated circuit device and also provide a process sequence used for forming the structure. SOLUTION: A trench structure wherein a trench is demarcated in a semiconductor substrate 100 includes a trench wall, a silicon buried plate 14 doped with conductive species existing in part of the semiconductor substrate around the trench wall, and a silicon structure with texture formed along part of the trench wall. This trench capacitor has improved capacitance by including a capacitor plate constituted of semispherical silicons with texture.

公开(公告)号：JPH11260935A

公开(公告)日：1999-09-24

申请号：JP4799

申请日：1999-01-04

Applicant: IBM

Inventor： BRONNER GARY BELA ,  GAMBINO JEFFREY P ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To manufacture a cap self-aligned on a gate conductor, and realize a two actional function for selectively applying P doping and N doping to the gate conductor. SOLUTION: A selected number of gate structures having self-aligned insulating layers 2 and 4 are doped by a first conductive type dopant through at least one sidewall of the gate structure. Thus, one gate structure is doped with the first conductive dopant, and another gate structure is doped with a second and different conductive dopant in this gate structural array. Therefore, a two actional function can be given.

公开(公告)号：DE69939451D1

公开(公告)日：2008-10-16

申请号：DE69939451

申请日：1999-10-15

Applicant: IBM

Inventor： RADENS CARL J ,  WEYBRIGHT MARY E

IPC: H01L27/108 ,  H01L21/8242

Abstract: A memory cell structure uses field-effect controlled majority carrier depletion of a buried strap region for controlling the access to a trench-cell capacitor. The buried strap connection between the trench capacitor and the bitline contact (CB) in regions where the deep trench pattern intersects the active area of the device. The upper section of the trench contains a single crystalline material to minimize the amount of leakage. The memory cell structure includes a field-effect switch having a gate terminal which induces the depletion region in the substrate and the top of the trench, the extent of the depletion region varying as a function of a voltage applied to the gate terminal; a storage device that includes an isolation collar (400) and a capacitor, the depletion region overlapping the isolation collar when the field-effect switch is in an off- state, and the depletion region does not overlap the isolation collar when the field effect switch is in an on-state.

公开(公告)号：DE60106256D1

公开(公告)日：2004-11-11

申请号：DE60106256

申请日：2001-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KUNKEL GERHARD ,  BUTT SHAHID ,  RADENS CARL J

IPC: G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/00

Abstract: A dynamic random access memory is formed in a silicon chip in arrays of clusters, each of four cells in a single active area. Each active area is cross-shaped with vertical trenches at the four ends of the two crossbars. The central region of the active area where the two crossbars intersect serves as the common base region of the four transistors of the cluster. The top of the base region serves as a common drain for the four transistors and each transistor has a separate channel along the wall of its associated vertical trench that provides its storage capacitor. Each cluster includes a common bit line and four separate word-line contacts.

公开(公告)号：DE69934357D1

公开(公告)日：2007-01-25

申请号：DE69934357

申请日：1999-06-17

Applicant: SIEMENS AG ,  IBM

Inventor： GAMBINO JEFFREY P ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L21/8242 ,  H01L27/108

Abstract: Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.