公开(公告)号：EP1128427A8

公开(公告)日：2001-11-28

申请号：EP01301600

申请日：2001-02-22

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM ,  TOSHIBA KK

Inventor： DIVAKARUNI RUNI ,  LA ROSA GIUSEPPE ,  WEYBRIGHT MARY E ,  KATSUMATA RYOTA ,  RENGARAJAN RAJESH

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L21/823878 ,  H01L21/26506 ,  H01L21/28123 ,  H01L21/823481 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/7838

Abstract: P-type metal-oxide semiconductor field effect transistor (PMOSFET) devices have a characteristic property known as threshold voltage. This threshold voltage may consist of separate threshold voltages associated with the main portion of the gate region of the device and with the sidewall corner of the device. Under some conditions, the threshold behavior in the sidewall corner region of the device may dominate the performance of the device, not necessarily in the manner intended by the designer of the device. A method of controlling threshold voltage behavior is described. In particular, ion implantation of nitrogen in the gate sidewall region of the device can provide such control. Devices made by this method are also described.

公开(公告)号：JP2000138354A

公开(公告)日：2000-05-16

申请号：JP29115799

申请日：1999-10-13

Applicant: IBM

Inventor： RADENS CARL J ,  WEYBRIGHT MARY E

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell structure, where depletion of majority carrier controlled by the field effect of an embedded strap region that controls access to a trench cell capacitor is used. SOLUTION: A memory cell structure is equipped with a field effect switch provided with a gate terminal 1000 possessed of a trench upper part and a depletion region in a substrate. The range of the depletion region is varied as function of a voltage applied to the gate terminal. Furthermore, a memory device having an isolation collar 400 and a capacitor is provided, and when a field effect switch is at an off-state, a depletion region is superposed on the isolation collar 400, and the depletion region will not be superposed on the isolation collar, when the field effect switch is at an on-state.

公开(公告)号：WO0245134A3

公开(公告)日：2003-04-03

申请号：PCT/US0151214

申请日：2001-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HORN PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/60 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

Abstract translation: 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

公开(公告)号：AT407452T

公开(公告)日：2008-09-15

申请号：AT99308160

申请日：1999-10-15

Applicant: IBM

Inventor： RADENS CARL J ,  WEYBRIGHT MARY E

IPC: H01L27/108 ,  H01L21/8242

Abstract: A memory cell structure uses field-effect controlled majority carrier depletion of a buried strap region for controlling the access to a trench-cell capacitor. The buried strap connection between the trench capacitor and the bitline contact (CB) in regions where the deep trench pattern intersects the active area of the device. The upper section of the trench contains a single crystalline material to minimize the amount of leakage. The memory cell structure includes a field-effect switch having a gate terminal which induces the depletion region in the substrate and the top of the trench, the extent of the depletion region varying as a function of a voltage applied to the gate terminal; a storage device that includes an isolation collar (400) and a capacitor, the depletion region overlapping the isolation collar when the field-effect switch is in an off- state, and the depletion region does not overlap the isolation collar when the field effect switch is in an on-state.

公开(公告)号：DE60133214D1

公开(公告)日：2008-04-24

申请号：DE60133214

申请日：2001-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HOH PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/8242 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8239

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

公开(公告)号：DE60133214T2

公开(公告)日：2009-04-23

申请号：DE60133214

申请日：2001-11-13

Applicant: IBM ,  QIMONDA AG

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HOH PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/8242 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8239

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

公开(公告)号：DE69939451D1

公开(公告)日：2008-10-16

申请号：DE69939451

申请日：1999-10-15

Applicant: IBM

Inventor： RADENS CARL J ,  WEYBRIGHT MARY E

IPC: H01L27/108 ,  H01L21/8242

Abstract: A memory cell structure uses field-effect controlled majority carrier depletion of a buried strap region for controlling the access to a trench-cell capacitor. The buried strap connection between the trench capacitor and the bitline contact (CB) in regions where the deep trench pattern intersects the active area of the device. The upper section of the trench contains a single crystalline material to minimize the amount of leakage. The memory cell structure includes a field-effect switch having a gate terminal which induces the depletion region in the substrate and the top of the trench, the extent of the depletion region varying as a function of a voltage applied to the gate terminal; a storage device that includes an isolation collar (400) and a capacitor, the depletion region overlapping the isolation collar when the field-effect switch is in an off- state, and the depletion region does not overlap the isolation collar when the field effect switch is in an on-state.