公开(公告)号：DE50205437D1

公开(公告)日：2006-02-02

申请号：DE50205437

申请日：2002-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

IPC: G11C15/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108

Abstract: The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

公开(公告)号：DE10128718B4

公开(公告)日：2005-10-06

申请号：DE10128718

申请日：2001-06-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  ALSMEIER JOHANN

IPC: H01L21/8242 ,  H01L27/108

Abstract: A memory cell has a selection transistor and a trench capacitor. An upper capacitor electrode of the trench capacitor, in the region of an insulating collar, has a metallic section, and that section of the upper electrode that makes contact with a storage dielectric is of a non-metallic form, in particular containing polysilicon. A buried strap, which connects the upper electrode to the select transistor, is of a non-metallic form, in particular formed of polysilicon.

公开(公告)号：DE10162900C1

公开(公告)日：2003-07-31

申请号：DE10162900

申请日：2001-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAENGER ANNETTE ,  SELL BERNHARD ,  BIRNER ALBERT ,  GOLDBACH MATTHIAS

IPC: H01L21/288 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: The invention relates to a method for fabricating low-resistance electrodes in trench capacitors, and includes steps of: providing a wafer; producing trenches in the wafer; introducing the wafer into an electrolyte solution including a salt of an electrically conductive material; and electrically contact-connecting the wafer and applying a voltage between the wafer and a counterelectrode configured in the electrolyte solution to electrodeposit at least sections of the electrically conductive material in the trenches. The electrodeposition of the electrode material enables a uniform layer thickness along all regions of the trench wall.

公开(公告)号：DE10136400A1

公开(公告)日：2003-02-27

申请号：DE10136400

申请日：2001-07-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  MOLL PETER

IPC: C23C16/32 ,  C23C16/44 ,  C23C16/455 ,  C23C16/56 ,  H01L21/285 ,  H01L21/8242 ,  H01L27/108

Abstract: At least a partial layer of an upper capacitor electrode is formed by metal carbide, preferably by a transition metal carbide. In one embodiment, the metal carbide layer is formed by depositing an alternating sequence of metal-containing layers and carbon-containing layers on top of one another and then subjecting them to a heat treatment, in such a manner that they mix with one another. The patterning of the layer sequence can be carried out before the carbide formation step.

公开(公告)号：DE10136716A1

公开(公告)日：2003-02-13

申请号：DE10136716

申请日：2001-07-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN ,  SCHLOESSER TILL

IPC: H01L25/065 ,  H01L27/108 ,  H01L23/50

Abstract: The manufacturing method uses semiconductor technology for provision of at least one capacitor and transistor for a memory cell of a memory cell field (31), together with a control and evaluation circuit (21), positioned vertically above the memory cells of the memory cell field. The memory cell field and the control and evaluation circuit are incorporated in respective overlapping surface regions (2,3) which are at least partially coupled together. An Independent claim for a dynamic random-access memory element is also included.

公开(公告)号：DE10120053A1

公开(公告)日：2002-11-14

申请号：DE10120053

申请日：2001-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  SELL BERNHARD ,  SAENGER ANNETTE

IPC: H01L21/8242 ,  H01L27/108

Abstract: The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.

公开(公告)号：DE10121132A1

公开(公告)日：2002-10-31

申请号：DE10121132

申请日：2001-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  HECHT THOMAS ,  SAENGER ANNETTE

IPC: C23C16/02 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/3205

Abstract: The invention relates to a method for production of a metallic or metal-containing layer (5) by using a pre-cursor on a silicon- or germanium-containing layer, of, in particular, an electronic component, whereby an intermediate layer (4) is applied to the silicon- or germanium-containing layer (3) before the use of the pre-cursor. Said intermediate layer forms a diffusion barrier for at least those elements of the pre-cursor which would etch the silicon- or germanium-containing layer and is itself resistant to etching by the pre-cursor.