公开(公告)号：SG52166A1

公开(公告)日：1998-09-28

申请号：SG1995001261

申请日：1995-08-31

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M

IPC: H01L21/265 ,  H01L21/332 ,  H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L29/10 ,  H01L29/41 ,  H01L29/417 ,  H01L29/739 ,  H01L29/744 ,  H01L29/749 ,  H01L29/78

Abstract: A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask (33) to sequentially form a cell body (50) and a source region (51) within the cell body (50), and a second mask step to form, by a silicon etch, a central opening (80,81) in the silicon surface at each cell and to subsequently undercut the oxide (60) surrounding the central opening (80,81). A contact layer (84) then fills the openings (80,81) of each cell to connect together the body (50) and source regions (51). Only one critical mask alignment step is used in the process.

公开(公告)号：ITMI962099A1

公开(公告)日：1998-04-10

申请号：ITMI962099

申请日：1996-10-10

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M ,  WAGERS KENNETH

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/765 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

Abstract: A termination structure for semiconductor devices and a process for fabricating the termination structure are described which prevent device breakdown at the peripheries of the device. The termination structure includes a polysilicon field plate located atop a portion of a field oxide region and which, preferably, overlays a portion of the base region. The field plate may also extend slightly over the edge of the field oxide to square off the field oxide taper. The termination structure occupies minimal surface area of the chip and is fabricated without requiring additional masking steps.

公开(公告)号：CZ9700629A3

公开(公告)日：1997-11-12

申请号：CZ62997

申请日：1995-08-17

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/332 ,  H01L21/336 ,  H01L21/768 ,  H01L29/10 ,  H01L29/41 ,  H01L29/417 ,  H01L29/739 ,  H01L29/744 ,  H01L29/749 ,  H01L29/78

CPC classification number: H01L29/7802 ,  H01L29/1095 ,  H01L29/41716 ,  H01L29/41766 ,  H01L29/66363 ,  H01L29/66727 ,  H01L29/7396

Abstract: A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask (33) to sequentially form a cell body (50) and a source region (51) within the cell body (50), and a second mask step to form, by a silicon etch, a central opening (80,81) in the silicon surface at each cell and to subsequently undercut the oxide (60) surrounding the central opening (80,81). A contact layer (84) then fills the openings (80,81) of each cell to connect together the body (50) and source regions (51). Only one critical mask alignment step is used in the process.

公开(公告)号：PL319098A1

公开(公告)日：1997-07-21

申请号：PL31909895

申请日：1995-08-17

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/332 ,  H01L21/336 ,  H01L21/768 ,  H01L29/10 ,  H01L29/41 ,  H01L29/417 ,  H01L29/739 ,  H01L29/744 ,  H01L29/749 ,  H01L29/78

Abstract: A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask (33) to sequentially form a cell body (50) and a source region (51) within the cell body (50), and a second mask step to form, by a silicon etch, a central opening (80,81) in the silicon surface at each cell and to subsequently undercut the oxide (60) surrounding the central opening (80,81). A contact layer (84) then fills the openings (80,81) of each cell to connect together the body (50) and source regions (51). Only one critical mask alignment step is used in the process.

公开(公告)号：NO970934L

公开(公告)日：1997-04-24

申请号：NO970934

申请日：1997-02-28

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M

IPC: H01L21/265 ,  H01L21/332 ,  H01L21/336 ,  H01L21/768 ,  H01L21/28 ,  H01L29/10 ,  H01L29/41 ,  H01L29/417 ,  H01L29/739 ,  H01L29/744 ,  H01L29/749 ,  H01L29/78 ,  H01L21/335 ,  H01L21/266 ,  H01L21/31 ,  H01L29/772

Abstract: A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask (33) to sequentially form a cell body (50) and a source region (51) within the cell body (50), and a second mask step to form, by a silicon etch, a central opening (80,81) in the silicon surface at each cell and to subsequently undercut the oxide (60) surrounding the central opening (80,81). A contact layer (84) then fills the openings (80,81) of each cell to connect together the body (50) and source regions (51). Only one critical mask alignment step is used in the process.

公开(公告)号：FI970850A0

公开(公告)日：1997-02-28

申请号：FI970850

申请日：1997-02-28

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/332 ,  H01L21/336 ,  H01L21/768 ,  H01L29/10 ,  H01L29/41 ,  H01L29/417 ,  H01L29/739 ,  H01L29/744 ,  H01L29/749 ,  H01L29/78 ,  H01L

Abstract: A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask (33) to sequentially form a cell body (50) and a source region (51) within the cell body (50), and a second mask step to form, by a silicon etch, a central opening (80,81) in the silicon surface at each cell and to subsequently undercut the oxide (60) surrounding the central opening (80,81). A contact layer (84) then fills the openings (80,81) of each cell to connect together the body (50) and source regions (51). Only one critical mask alignment step is used in the process.

公开(公告)号：DE19534388A1

公开(公告)日：1996-03-21

申请号：DE19534388

申请日：1995-09-15

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M

IPC: H01L29/78 ,  H01L27/04 ,  H01L29/739 ,  H03K17/04 ,  H03K17/082 ,  H03K17/567

Abstract: The module includes an IGBT component of a bipolar PNP transistor (10), and two MOSFETs (11,40). The source region of one MOSFET (11) is coupled to the PNP transistor base region. This MOSFETs drain region and the PNP transistor emitter region are also interconnected and coupled to an emitter electrode (26). The other MOSFET (40), with source and drain regions and a gate electrode, has its source region connected to the collector electrode (38), with its drain region being linked to the source region of the initial MOSFET. Pref. the supply and switching of a gate voltage to the initial MOSFET gate electrode (G1) switches ON or OFF the PNP transistor.

公开(公告)号：GB2244400A

公开(公告)日：1991-11-27

申请号：GB9110324

申请日：1991-05-13

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M ,  TAM DAVID

IPC: H02M1/08 ,  G01R29/027 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003

Abstract: A pulse filter (93) is connected between a high voltage level shift circuit (59) which produces output pulses in a pattern determined by an input logic circuit (50-58) and the high side output circuit (94-101) which controls the production of power MOSFET or IGBT gate signals or the like. The pulse filter (93) immunizes the circuit against false operation duo to the fast dv/dt transients. The pulse filter (93) includes inverters for squaring an input signal and a CR delay element for increasing the rise time of the pulse so that pulses derived from transients are too small to drive the following stage and hence blocked. A pulse generator (80) derives set and reset pulses from the logic level of inputs (at 10, 11) and level shifted (at 59). Elements (61-70) relate to low voltage switching circuit. High voltage switching circuit (100, 101) drive power MOSFET's or IGBTs in a load circuit. Detectors (102, 70) prevent operation when supply voltage is low.

公开(公告)号：GB2184602B

公开(公告)日：1988-05-25

申请号：GB8700582

申请日：1987-01-12

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M ,  COLLINS HOWARD WILLIAM

IPC: H01L27/06 ,  H01L21/8232 ,  H01L25/07 ,  H01L29/78 ,  H01L29/80 ,  H01L31/10 ,  H01L31/12 ,  H03K17/0412 ,  H03K17/78 ,  H03K17/785 ,  H01L31/16

Abstract: The gate capacitance of a Field effect transistor (24) used as a switch is rapidly charged via a diode (35) to turn the FET on, and is rapidly discharged to turn the FET off by a switching transistor (36) connected across the diode and the FET such that it becomes conductive only when the diode becomes reverse biased, thereby providing a discharge path for the gate capacitance. The circuit is used in a photovoltaic relay, the FET being turned on by a photovoltaic isolator (20) having a LED 21 energised by an input signal optically coupled to and dielectrically isolated from a series-connected stack of photo diodes connected to the switching FET, which may comprise a bilateral semiconductor FET (BOSFET).

公开(公告)号：DE19918198B4

公开(公告)日：2008-04-17

申请号：DE19918198

申请日：1999-04-22

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M

IPC: H01L29/78 ,  H01L21/336

Abstract: A low voltage P-channel power MOSFET using trench technology has an epitaxially deposited constant dopant concentration N-channel region 60 adjacent the side walls of a plurality of trenches 23, 24. The constant concentration channel region is deposited atop a P + substrate 20 and receives P + source regions 30-33 at the tops of each trench. The source contact 40 is connected to both source and channel regions for a unidirectional conduction device, or only to the source regions for a bidirectional device.