公开(公告)号：AU1930595A

公开(公告)日：1996-09-11

申请号：AU1930595

申请日：1995-02-24

Applicant: INTEL CORP

Inventor： DATTA SHAM ,  JOSHI JAYESH ,  KARDACH JAMES P

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/00

公开(公告)号：HK153695A

公开(公告)日：1995-10-06

申请号：HK153695

申请日：1995-09-28

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  NGUYEN CAU

IPC: G06F9/46 ,  G06F9/48

Abstract: A dedicated memory area is provided on a microprocessor system for storing a customizable system interrupt service routine, processor state data at the time of interruption and a halt indicator indicating the CPU was interrupted from a halt state. The dedicated memory area is normally not mapped as part of the main memory space, thereby keep it inaccessible to the operating system and applications. An unmaskable system supervisor interrupt having higher priority than all other maskable and unmaskable interrupts is added to the CPU interrupts. The halt state indicator is set by the added interrupt of the CPU is in a halt state at the time of interruption. A RESUME instruction is added to the CPU instructions to provide recovery of the CPU to the state before it was interrupted. The Halt instruction is re-executed by the RESUME instruction if the halt state indicator remains set at the time of restoration. As a result, a system integrator or OEM may provide transparent system level interrupts with automated halt state restart that will operate reliably in any operating environment, and be relieved of the burden of managing halt state restart.

公开(公告)号：HK66295A

公开(公告)日：1995-05-12

申请号：HK66295

申请日：1995-05-04

Applicant: INTEL CORP

Inventor： REDDY CHANDRASHEKAR M ,  HIROSE SCOTT D ,  CHO SUNG-SOO ,  KARDACH JAMES P ,  FARRER STEVEN M ,  ROBERTS MEELING

IPC: G06F1/04 ,  G06F1/32 ,  G06F15/78 ,  G11C11/401 ,  G11C11/406

Abstract: A power suspend mode activates a slow DRAM refresh in a computer system with a limited source of power. The power suspend mode reduces the power consumed by the computer system while preserving the contents of memory. The cyclic refresh of DRAM using a slow refresh clock substantially reduces the power consumed while the computer is suspended. This technique is particularly useful for battery powered portable computer systems. When an external or internal condition causes the computer system to transition to a power down mode, an IO subsystem notifies the CPU which sets control bits in the IO subsystem and a video subsystem. The IO subsystem then begins to generate a slow DRAM refresh pulse. Once the CPU and video subsystem sense the power suspend mode activation, the system memory and video memory are refreshed using the slow refresh clock. The power consumed during the refresh process is thereby greatly reduced. When a resume signal is received by the IO subsystem, the slow refresh clock is terminated and the system memory and video memory are again refreshed using a normal faster clock.

公开(公告)号：GB2259166B

公开(公告)日：1995-05-03

申请号：GB9217580

申请日：1992-08-19

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  NGUYEN CAU ,  SIVAMANI KAMESWARAN

IPC: G06F9/46 ,  G06F9/48

公开(公告)号：AU8908691A

公开(公告)日：1992-05-20

申请号：AU8908691

申请日：1991-10-11

Applicant: INTEL CORP

Inventor： REDDY CHANDRASHEKAR M ,  HIROSE SCOTT D ,  CHO SUNG-SOO ,  KARDACH JAMES P ,  FARRER STEVEN M ,  ROBERTS MEELING

IPC: G06F1/04 ,  G06F1/32 ,  G06F15/78 ,  G11C11/401 ,  G11C11/406 ,  G06F1/26

Abstract: A power suspend mode activates a slow DRAM refresh in a computer system with a limited source of power. The power suspend mode reduces the power consumed by the computer system while preserving the contents of memory. The cyclic refresh of DRAM using a slow refresh clock substantially reduces the power consumed while the computer is suspended. This technique is particularly useful for battery powered portable computer systems. When an external or internal condition causes the computer system to transition to a power down mode, an IO subsystem notifies the CPU which sets control bits in the IO subsystem and a video subsystem. The IO subsystem then begins to generate a slow DRAM refresh pulse. Once the CPU and video subsystem sense the power suspend mode activation, the system memory and video memory are refreshed using the slow refresh clock. The power consumed during the refresh process is thereby greatly reduced. When a resume signal is received by the IO subsystem, the slow refresh clock is terminated and the system memory and video memory are again refreshed using a normal faster clock.