公开(公告)号：HK1066128A1

公开(公告)日：2005-03-11

申请号：HK04109016

申请日：2004-11-15

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L

IPC: H04L20060101 ,  G06F1/025 ,  H03M7/00 ,  H04J11/00 ,  H04J13/00 ,  H04J13/12 ,  H04L9/00 ,  H04L27/30

Abstract: A pseudorandom code generator comprising a code generator configured to generate a series of 2 M M-bit wide binary codes starting from a lowest bit to a highest bit; an index code selector configured to select an M-bit wide binary index code corresponding to an index number of a pseudorandom code among a set of pseudorandom codes; a logical operator configured to perform a logical operation between each code generated by the code generator and the index code selected by the index code selector in order to generate a 2 M -bit wide pseudorandom code; and a code reverser configured to reverse an order of bits generated by the code generator from a least significant bit to a most significant bit.

公开(公告)号：AR039290A1

公开(公告)日：2005-02-16

申请号：ARP030101272

申请日：2003-04-11

Applicant: INTERDIGITAL TECH CORP

Inventor： KAEWELL JOHN DAVID JR ,  BERGHIUS TIMOTHY ,  MEYER JAN ,  BOHNHOFF PETER ,  REZNIK ALEXANDER ,  HEPLER EDWARD L ,  HACKETT WILLIAM C ,  KOCH MICHAEL ,  DAVID S BASS

IPC: H04B7/04 ,  H04B7/08 ,  H04B7/26 ,  H04B1/06 ,  H04B7/216 ,  H04J13/00

Abstract: Un receptor de Nodo B/estación base comprende al menos una antena para recibir senales. Cada finger de un grupo de fingers Rake reconfigurable recupera un componente de trayectoria múltiple de un usuario y se le asigna un código del usuario, una fase de código del componente de trayectoria múltiple y una antena de al menos una antena. Una interfase de grupo de finger Rake/antena, le provee a cada finger del grupo Rake, una salida de la antena asignada a ese finger Rake. Un combinador combina los componentes de trayectoria múltiple recuperados para que un usuario produzca datos del usuario.

公开(公告)号：NO20041357A

公开(公告)日：2004-04-01

申请号：NO20041357

申请日：2004-04-01

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  STARSINIC MICHAEL F

IPC: G06F11/10 ,  H03M13/29 ,  H03M13/39 ,  H03M13/45 ,  G06N5/04

CPC classification number: H03M13/3905 ,  H03M13/3972 ,  H03M13/6505

公开(公告)号：AU2003223595A8

公开(公告)日：2003-11-03

申请号：AU2003223595

申请日：2003-04-15

Applicant: INTERDIGITAL TECH CORP

Inventor： BASS DAVID S ,  CASTOR DOUGLAS R ,  MCCLELLAN GEORGE W ,  LEVI ALAN M ,  DESAI BINISH ,  HEPLER EDWARD L ,  STARSINIC MICHAEL F

IPC: H04J1/00 ,  H04B1/40 ,  H04B1/707 ,  H04B7/26 ,  H04J3/00 ,  H04J4/00 ,  H04L1/00 ,  H04L1/08 ,  H04L12/56 ,  H04W28/18 ,  H04W74/02 ,  H04W80/00 ,  H04W88/02

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (305,307), a composite channel processing block (303,309) and a chip rate processing block (301,311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

公开(公告)号：AU2003224918A8

公开(公告)日：2003-10-27

申请号：AU2003224918

申请日：2003-04-11

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  BERGHIUS TOMOTHY ,  BOHNHOFF PETER ,  HACKETT WILLIAM C ,  KAEWELL JOHN DAVID JR ,  MEYER JAN ,  KOCH MICHAEL ,  REZNIK ALEXANDER ,  BASS DAVID S

IPC: H04B7/04 ,  H04B7/08 ,  H04B7/26 ,  H04B1/707

Abstract: A Node-B/base station receiver comprises at least one antenna for receiving signals. Each finger of a pool of reconfigurable Rake fingers recovers a multipath component of a user and is assigned a code of the user, a code phase of the multipath component and an antenna of the at least one antenna. An antenna/Rake finger pool interface provides each finger of the Rake pool an output of the antenna assigned to that Rake finger. A combiner combines the recovered multipath components for a user to produce data of the user.

公开(公告)号：MY142326A

公开(公告)日：2010-11-15

申请号：MYPI20083764

申请日：2005-05-20

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  GAZDA ROBERT G

IPC: G06F12/00 ,  G06F21/00 ,  H04L9/00 ,  H04L29/06

Abstract: A DATA PROCESSING SYSTEM (100) CIPHERS AND TRANSFERS DATA BETWEEN A FIRST MEMORY UNIT AND A SECOND MEMORY UNIT, SUCH AS, FOR EXAMPLE, BETWEEN A SHARE MEMORY ARCHITECTURE (SMA) STATIC RANDOM ACCESS MEMORY (SRAM) AND A DOUBLE DATA RATE (DDR) SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM). THE SYSTEM INCLUDES A CIPHERING ENGINE (130) AND A DATA-MOVER CONTROLLER (128). THE DATA-MOVER CONTROLLER INCLUDES AT LEAST ONE REGISTER HAVING A FIELD THAT SPECIFIES WHETHER OR NOT THE TRANSFERRED DATA SHOULD BE CIPHERED. IF THE FIELD SPECIFIES THAT THE TRANSFERRED DATA SHOULD BE CIPHERED, THE FIELD ALSO SPECIFIES THE TYPE OF CIPHERING THAT IS TO BE PERFORMED, SUCH AS A THIRD GENERATION PARTNERSHIP PROJECT (3GPP) STANDARDIZED CONFIDENTIALLY CIPHER ALGORITHM "F8" OR INTEGRITY CIPHER ALGORITHM "F9". (FIGURE 1)

公开(公告)号：DE60233236D1

公开(公告)日：2009-09-17

申请号：DE60233236

申请日：2002-04-15

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  STARSINIC MICHAEL F

IPC: G06F11/10 ,  G06N5/04 ,  H03M13/29 ,  H03M13/39 ,  H03M13/45

Abstract: The application relates to sliding-window maximum a posteriori MAP decoding. In a MAP decoder, a method for determining binary states of received signals comprises receiving data bits, each bit being accompanied by at least one parity bit, providing each received data bit and parity bit with an address (16a) of a calculated extrinsic value (14a) and associated intrinsic data and storing the data bits, the parity bits and the extrinsic value address in a first memory (12).

公开(公告)号：AR065977A2

公开(公告)日：2009-07-15

申请号：ARP080101443

申请日：2008-04-08

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  GAZDA ROBERT G

IPC: G06F21/00 ,  H04L9/00 ,  H04L29/06 ,  G06F13/00

Abstract: Un aparato para llevar a cabo el cifrado y la transferencia de datos entre una primera unidad de memoria y una segunda unidad de memoria, aparato que comprende: un controlador de desplazamiento de datos que incluye al menos un registro que tiene unprimer campo que especifica si los datos transferidos deben ser cifrados o no; y un procesador eléctricamente acoplado a la primera unidad de memoria y a la segunda unidad de memoria para escribir un bloque de control en la primera unidad dememoria, incluyendo el bloque de control parámetros de control que se necesitan para configurar el controlador de desplazamiento de datos, y para dar salida a una senal de control al controlador de desplazamiento de datos para iniciar una operacionde movimiento de datos; en donde el controlador de desplazamiento de datos recupera el bloque de control de la primera unidad de memoria en respuesta a la recepcion de la senal de control del procesador, y el controlador de desplazamiento de datosdetermina qué tipo de funcion se debe llevar a cabo en base a los parámetros de control en el bloque de control recuperado.

公开(公告)号：MY137485A

公开(公告)日：2009-02-27

申请号：MYPI20031363

申请日：2003-04-11

Applicant: INTERDIGITAL TECH CORP

Inventor： KAEWELL JOHN DAVID JR ,  BERGHIUS TIMOTHY ,  MEYER JAN ,  BOHNHOFF PETER ,  REZNIK ALEXANDER ,  HEPLER EDWARD L ,  KOCH MICHAEL ,  HACKETT WILLIAM C ,  BASS DAVID S

IPC: H04B7/04 ,  H04B7/08 ,  H04B7/26

Abstract: A NODE-B/BASE STATION RECEIVER COMPRISES AT LEAST ONE ANTENNA (28) FOR RECEIVING SIGNALS. EACH FINGER OF A POOL OF RECONFIGURABLE RAKE FINGERS (32) RECOVERS A MULTIPATH COMPONENT (16) OF A USER AND IS ASSIGNED A CODE OF THE USER, A CODE PHASE OF THE MULTIPATH COMPONENT AND AN ANTENNA OF THE AT LEAST ONE ANTENNA. AN ANTENNA/RAKE FINGER POOL INTERFACE (30) PROVIDES EACH FINGER OF THE RAKE POOL AN OUTPUT OF THE ANTENNA ASSIGNED TO THAT RAKE FINGER. A COMBINER (42) COMBINES THE RECOVERED MULTIPATH COMPONENTS FOR A USER TO PRODUCE DATA OF THE USER.

公开(公告)号：AU2005332284B8

公开(公告)日：2008-08-14

申请号：AU2005332284

申请日：2005-05-06

Applicant: INTERDIGITAL TECH CORP

Inventor： GAZDA ROBERT G ,  HEPLER EDWARD L

IPC: H04L9/18 ,  G06F12/00 ,  G06F13/00 ,  G06F21/00 ,  H04L9/00 ,  H04L29/06

Abstract: A data processing system ciphers and transfers data between a first memory unit and a second memory unit, such as, for example, between a share memory architecture (SMA) static random access memory (SRAM) and a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The system includes a ciphering engine and a data-mover controller. The data-mover controller includes at least one register having a field that specifies whether or not the transferred data should be ciphered. If the field specifies that the transferred data should be ciphered, the field also specifies the type of ciphering that is to be performed, such as a third generation partnership project (3GPP) standardized confidentially cipher algorithm “f8” or integrity cipher algorithm “f9”.