公开(公告)号：US12079155B2

公开(公告)日：2024-09-03

申请号：US17428216

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Selvakumar Panneer ,  Saurabh Tangri ,  Ben Ashbaugh ,  Scott Janus ,  Abhishek Appu ,  Varghese George ,  Ravishankar Iyer ,  Nilesh Jain ,  Pattabhiraman K ,  Altug Koker ,  Mike MacPherson ,  Josh Mastronarde ,  Elmoustapha Ould-Ahmed-Vall ,  Jayakrishna P. S ,  Eric Samson

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

公开(公告)号：US20240007414A1

公开(公告)日：2024-01-04

申请号：US18039166

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Nilesh Jain ,  Rajesh Poornachandran ,  Eriko Nurvitadhi ,  Anahita Bhiwandiwalla ,  Juan Pablo Munoz ,  Ravishankar Iyer ,  Chaunte W. Lacewell

IPC: H04L47/726 ,  H04L47/2425 ,  H04L47/765

CPC classification number: H04L47/726 ,  H04L47/2425 ,  H04L47/765

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to optimize resources in edge networks. An example apparatus includes agent managing circuitry to invoke an exploration agent to identify platform resource devices, select a first one of the identified platform resource devices, and generate first optimization metrics for the workload corresponding to the first one of the identified platform resource devices, the first optimization metrics corresponding to a first path. The example agent is to further select a second one of the identified platform resource devices, generate second optimization metrics for the workload corresponding to the second one of the identified platform resource devices, the second optimization metrics corresponding to a second path. The example apparatus also includes benchmark managing circuitry to embed second semantic information to the workload, the second semantic information including optimized graph information and platform structure information corresponding to the second one of the identified platform resource devices, and reconfiguration managing circuitry to select the first path or the second path during runtime based on (a) service level agreement (SLA) information and (b) utilization information corresponding to the first and second identified platform resource devices.

公开(公告)号：US11531562B2

公开(公告)日：2022-12-20

申请号：US17077796

申请日：2020-10-22

Applicant: Intel Corporation

Inventor： Matthew Fleming ,  Edwin Verplanke ,  Andrew Herdrich ,  Ravishankar Iyer

IPC: G06F9/46 ,  G06F9/455 ,  G06F11/30

Abstract: Systems, methods, and apparatuses for resource monitoring identification reuse are described. In an embodiment, a system comprising a hardware processor core to execute instructions storage for a resource monitoring identification (RMID) recycling instructions to be executed by a hardware processor core, a logical processor to execute on the hardware processor core, the logical processor including associated storage for a RMID and state, are described.

公开(公告)号：US20220116284A1

公开(公告)日：2022-04-14

申请号：US17645742

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Ravishankar Iyer ,  Nilesh Jain ,  Juan Munoz ,  Eriko Nurvitadhi ,  Anahita Bhiwandiwalla ,  Rajesh Poornachandran

IPC: H04L41/5003 ,  G06N3/10

Abstract: Methods, apparatus, systems, and articles of manufacture for dynamic XPU hardware-aware deep learning model management are disclosed. An example method includes extracting a plurality of models from a dataset, respective ones of the plurality of models optimized for a selected quality of service (QoS) objective of a plurality of QoS objectives, identifying a plurality of feature differences between respective ones of the plurality of models, and identifying a plurality of feature similarities between respective ones of the plurality of models.

公开(公告)号：US20220101597A1

公开(公告)日：2022-03-31

申请号：US17032348

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Selvakumar Panneer ,  Mrutunjayya Mrutunjayya ,  Carl S. Marshall ,  Ravishankar Iyer ,  Zack Waters

IPC: G06T15/80 ,  G06T15/00 ,  G06T15/10 ,  G06N3/08

Abstract: An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.

公开(公告)号：US11127107B2

公开(公告)日：2021-09-21

申请号：US16588855

申请日：2019-09-30

Applicant: Intel Corporation

Inventor： Ravishankar Iyer ,  Selvakumar Panneer ,  Carl S. Marshall ,  John Feit ,  Venkat R. Gokulrangan

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  A63F13/358

Abstract: An apparatus and method for scheduling threads on local and remote processing resources. For example, one embodiment of an apparatus comprises: a local graphics processor to execute threads of an application; graphics processor virtualization circuitry and/or logic to generate a virtualized representation of a local processor; a scheduler to identify a first subset of the threads for execution on a local graphics processor and a second subset of the threads for execution on a virtualized representation of a local processor; the scheduler to schedule the first subset of threads on the local graphics processor and the second subset of the threads by transmitting the threads or a representation thereof to Cloud-based processing resources associated with the virtualized representation of the local processor; and the local graphics processor to combine first results of executing the first subset of threads on the local graphics processor with second results of executing the second subset of threads on the Cloud-based processing resources to render an image frame.

公开(公告)号：US10936490B2

公开(公告)日：2021-03-02

申请号：US15634785

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Stephen R. Van Doren ,  Ravishankar Iyer ,  Eric R. Wehage ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Jeffrey D. Chamberlain ,  Julius Mandelblat ,  Yen-Cheng Liu ,  Stephen T. Palermo ,  Tsung-Yuan C. Tai

IPC: G06F12/08 ,  G06F12/0811 ,  G06F13/42 ,  G06F9/455 ,  G06F9/50 ,  G06F12/1009 ,  G06F13/16

Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

公开(公告)号：US10664039B2

公开(公告)日：2020-05-26

申请号：US16043738

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Rameshkumar G. Illikkal ,  Ravishankar Iyer ,  Sadagopan Srinivasan ,  Jaideep Moses ,  Srihari Makineni

IPC: G06F1/3293 ,  G06F9/50 ,  G06F1/3287 ,  G06F9/4401 ,  G06F13/24 ,  H04W52/02 ,  H04W88/02 ,  G06F1/3206 ,  G06F12/084

Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

公开(公告)号：US10331492B2

公开(公告)日：2019-06-25

申请号：US15676948

申请日：2017-08-14

Applicant: INTEL CORPORATION

Inventor： Andrew J. Herdrich ,  Kapil Sood ,  Nrupal R. Jani ,  David J. Harriman ,  Mesut A. Ergin ,  Scott P. Dubal ,  Ravishankar Iyer

IPC: G06F9/50

Abstract: Examples may include techniques to coordinate the sharing of resources among virtual elements, including service chains, supported by a shared pool of configurable computing resources based on relative priority among the virtual element and service chains. Information including indications of the performance of the service chains and also the relative priority of the service chains may be received. The resource allocation of portions of the shared pool of configurable computing resources supporting the service chains can be adjusted based on the received performance and priority information.

公开(公告)号：US10275222B2

公开(公告)日：2019-04-30

申请号：US15070988

申请日：2016-03-15

Applicant: Intel Corporation

Inventor： Glen J. Anderson ,  Rebecca A. Chierichetti ,  Meng Shi ,  Yevgeniy Y. Yarmosh ,  Mark R. Francis ,  Ravishankar Iyer ,  Reese Bowes ,  Ankur Agrawal

IPC: G06F9/44 ,  G06F8/20 ,  G06F17/50

Abstract: Apparatuses, methods and storage medium associated with a model compute system for physical programming are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify first rules associated with one or more physical subcomponents, e.g., blocks, tiles, or the like, or combinations thereof, assembled in a constructed model in a first control modality, wherein at least one first rule defines a first predetermined behavior of the constructed model, and determine a first program stack for execution by the model compute system based on the first rules associated with the one or more physical subcomponents. Other embodiments may be described and/or claimed.