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    PIEZOELECTRIC RESONATOR HAVING COMBINED THICKNESS AND WIDTH VIBRATIONAL MODES
    42.
    发明申请
    PIEZOELECTRIC RESONATOR HAVING COMBINED THICKNESS AND WIDTH VIBRATIONAL MODES 审中-公开
    具有组合厚度和宽度振动模式的压电谐振器

    公开(公告)号：WO2013044262A1

    公开(公告)日：2013-03-28

    申请号：PCT/US2012/056962

    申请日：2012-09-24

    Applicant: QUALCOMM Incorporated ,  ZUO, Chengjie ,  LO, Chi Shun ,  JOO, Sanghoon ,  YUN, Changhan ,  KIM, Jonghae

    Inventor： ZUO, Chengjie ,  LO, Chi Shun ,  JOO, Sanghoon ,  YUN, Changhan ,  KIM, Jonghae

    IPC: H03H9/56 ,  H03H9/02

    CPC classification number: H03H9/02157 ,  H03H9/02062 ,  H03H9/56

    Abstract: A method and apparatus for a piezoelectric resonator (200) having combined thickness (220T) and width (220W) vibrational modes are disclosed. A piezoelectric resonator may include a piezoelectric substrate (210) and a first electrode (205) coupled to a first surface of the piezoelectric substrate. The piezoelectric resonator may further include a second electrode (215) coupled to a second surface of the piezoelectric substrate, where the first surface and the second surface are substantially parallel and define a thickness dimension of the piezoelectric substrate. Furthermore, the thickness dimension (T) and the width (W) dimension of the piezoelectric substrate are configured to produce a resonance from a coherent combination of a thickness vibrational mode and a width vibrational mode when an excitation signal is applied to the electrodes.

    Abstract translation: 公开了一种具有组合厚度（220T）和宽度（220W）振动模式的压电谐振器（200）的方法和装置。 压电谐振器可以包括压电基板（210）和耦合到压电基板的第一表面的第一电极（205）。 压电谐振器还可以包括耦合到压电基板的第二表面的第二电极（215），其中第一表面和第二表面基本上平行并且限定压电基板的厚度尺寸。 此外，当将激励信号施加到电极时，压电基板的厚度尺寸（T）和宽度（W）尺寸被配置为从厚度振动模式和宽度振动模式的相干组合产生谐振。

    THREE DIMENSIONAL INDUCTOR AND TRANSFORMER DESIGN METHODOLOGY OF GLASS TECHNOLOGY
    44.
    发明申请
    THREE DIMENSIONAL INDUCTOR AND TRANSFORMER DESIGN METHODOLOGY OF GLASS TECHNOLOGY 审中-公开
    玻璃技术的三维电感器和变压器设计方法

    公开(公告)号：WO2011119947A1

    公开(公告)日：2011-09-29

    申请号：PCT/US2011/029978

    申请日：2011-03-25

    Applicant: QUALCOMM Incorporated ,  KIM, Jonghae ,  SHAH, Milind P. ,  LO, Chi Shun ,  LAN, Je-Hsiung ,  LI, Xia ,  NOWAK, Matthew Michael

    Inventor： KIM, Jonghae ,  SHAH, Milind P. ,  LO, Chi Shun ,  LAN, Je-Hsiung ,  LI, Xia ,  NOWAK, Matthew Michael

    IPC: H01L21/02 ,  H01L23/64 ,  H01L27/08 ,  H01L27/12 ,  H01L21/84 ,  H01F17/00 ,  H01F5/00 ,  H01L21/68

    CPC classification number: H01L28/10 ,  H01F2017/004 ,  H01L21/84 ,  H01L23/645 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed is an inductor or transformer for use in integrated circuit devices that includes a high - resistivity substrate. The inductor (1100) includes a plurality of conductive traces (1110, 1112, 1114) around the substrate forming a continuous conductive path from a first to a second port. The conductive path can be solenoid- shaped. Some of the conductive traces can be formed during back- end- of - line processing or backside plating of an integrated circuit die. The transformer includes a first inductor with input and output ports, and a first continuous conductive path therebetween; and a second inductor with input and output ports, and a second continuous conductive path therebetween. The second inductor is independent of and electromagnetically coupled to the first inductor. The first and second conductive paths can be solenoid- shaped. The first conductive path can be interleaved with the second conductive path.

    Abstract translation: 公开了一种用于集成电路器件的电感器或变压器，其包括高电阻率衬底。 电感器（1100）包括围绕衬底的多个导电迹线（1110,1112,1114），其形成从第一端口到第二端口的连续导电路径。 导电路径可以是螺线管形的。 一些导电迹线可以在集成电路管芯的后端处理或背面电镀中形成。 变压器包括具有输入和输出端口的第一电感器和它们之间的第一连续导电路径; 以及具有输入和输出端口的第二电感器以及它们之间的第二连续导电路径。 第二电感器与第一电感器无关并与其电磁耦合。 第一和第二导电路径可以是螺线管形的。 第一导电路径可以与第二导电路径交错。

    HETEROGENEOUS TECHNOLOGY INTEGRATION
    45.
    发明申请
    HETEROGENEOUS TECHNOLOGY INTEGRATION 审中-公开
    异构技术整合

    公开(公告)号：WO2011119932A1

    公开(公告)日：2011-09-29

    申请号：PCT/US2011/029955

    申请日：2011-03-25

    Applicant: QUALCOMM Incorporated ,  KIM, Jonghae ,  GOUSEV, Evgeni P. ,  NOWAK, Matthew Michael

    Inventor： KIM, Jonghae ,  GOUSEV, Evgeni P. ,  NOWAK, Matthew Michael

    IPC: H01L25/065

    CPC classification number: H01L25/0655 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L29/0657 ,  H01L2224/16105 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/92227 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/00014

    Abstract: A heterogeneous integrated circuit having at least one tier made of multiple technologies and a method of making the heterogeneous integrated circuit. The heterogeneous integrated circuit includes a package substrate, a first die of a first technology, and a second die of a second technology, where the two dies are located in the same tier. One die can surround the other die. The heterogeneous integrated circuit can also include a wire-bond and/or horizontal micro-bump coupling the two dies. The heterogeneous integrated circuit can also include a wire bond or vertical micro-bump coupling one of the dies to the package substrate. The vertical micro-bump coupling can include a through-via. The two technologies can be any of various technologies including CMOS, glass, sapphire and quartz. One die can also be adjacent to the other die on the same tier and the two dies coupled using a horizontal micro-bump.

    Abstract translation: 具有由多种技术制成的至少一层的异质集成电路以及制造异质集成电路的方法。 异质集成电路包括封装衬底，第一技术的第一裸片和第二技术的第二裸片，其中两个裸片位于同一层。 一个模具可以围绕另一个模具。 异质集成电路还可以包括耦合两个管芯的引线接合和/或水平微凸块。 异质集成电路还可以包括引线接合或将一个管芯耦合到封装衬底的垂直微突起。 垂直微凸块耦合可以包括通孔。 这两种技术可以是包括CMOS，玻璃，蓝宝石和石英在内的各种技术。 一个管芯也可以在同一层上与另一个管芯相邻，并且两个管芯使用水平微型焊盘进行耦合。

    HIGH BREAKDOWN VOLTAGE EMBEDDED MIM CAPACITOR STRUCTURE
    46.
    发明申请
    HIGH BREAKDOWN VOLTAGE EMBEDDED MIM CAPACITOR STRUCTURE 审中-公开
    高突破电压嵌入式MIM电容结构

    公开(公告)号：WO2011017623A1

    公开(公告)日：2011-02-10

    申请号：PCT/US2010/044724

    申请日：2010-08-06

    Applicant: QUALCOMM Incorporated ,  KANG, Wootag ,  KIM, Jonghae

    Inventor： KANG, Wootag ,  KIM, Jonghae

    IPC: H01L21/02 ,  H01L27/08 ,  H01L27/10

    CPC classification number: H01L28/40 ,  H01L27/0805 ,  H01L27/101

    Abstract: Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device includes gate material (204) embedded in an insulator, (209) a plurality of metal contacts, (213) and a plurality of capacitors. (C1-C4) The plurality of capacitors includes a lower electrode, (217) a dielectric (219) formed so as to cover a surface of the lower electrode, and an upper electrode (221b, c) formed on the dielectric. Further, the plurality of contacts connects each of the lower electrodes of the plurality of capacitors to the gate material. The plurality of capacitors are connected in series via the gate material.

    Abstract translation: 提出了与多个高击穿电压嵌入式电容器相关的方法和装置。 半导体器件包括嵌入绝缘体中的栅极材料（204），（209）多个金属触点（213）和多个电容器。 （C1-C4）多个电容器包括下电极，（217）形成为覆盖下电极的表面的电介质（219）和形成在电介质上的上电极（221b，c）。 此外，多个触点将多个电容器中的每个下电极连接到栅极材料。 多个电容器通过栅极材料串联连接。

    RADIO-FREQUENCY INTEGRATED CIRCUITS (RFICS) INCLUDING A POROSIFIED SEMICONDUCTOR ISOLATION REGION TO REDUCE NOISE INTERFERENCE AND RELATED FABRICATION METHODS
    47.
    发明申请
    RADIO-FREQUENCY INTEGRATED CIRCUITS (RFICS) INCLUDING A POROSIFIED SEMICONDUCTOR ISOLATION REGION TO REDUCE NOISE INTERFERENCE AND RELATED FABRICATION METHODS 审中-公开

    公开(公告)号：WO2023049559A1

    公开(公告)日：2023-03-30

    申请号：PCT/US2022/074687

    申请日：2022-08-09

    Applicant: QUALCOMM INCORPORATED

    Inventor： DUTTA, Ranadeep ,  KIM, Jonghae ,  LAN, Je-Hsiung

    IPC: H01L21/76 ,  H01L29/06 ,  H01L21/762

    Abstract: Radio frequency (RF) circuits generate noise that can interfere with other RF circuits on the same semiconductor die. An isolation material disposed in an isolation region between a first active region of a first RF circuit and a second active region of a second RF circuit comprises a porosified region of the semiconductor material of the semiconductor die. The isolation material (e.g., porosified material) has a higher resistivity and lower permittivity than the semiconductor material to reduce transmission of noise interference between the first RF circuit and the second RF circuit. The isolation material in the isolation region of the semiconductor material comprises a porosity in the range 20% to 50% higher than the porosity of the semiconductor material in the first and second active regions. The porosified region has a lower permittivity and a higher resistivity than the non-porosified region to protect against the transmission of noise interference.

    3D INDUCTOR DESIGN USING BUNDLE SUBSTRATE VIAS
    49.
    发明申请
    3D INDUCTOR DESIGN USING BUNDLE SUBSTRATE VIAS 审中-公开

    公开(公告)号：WO2022265729A1

    公开(公告)日：2022-12-22

    申请号：PCT/US2022/026567

    申请日：2022-04-27

    Applicant: QUALCOMM INCORPORATED

    Inventor： KIM, Jonghae ,  LAN, Je-Hsiung ,  DUTTA, Ranadeep

    IPC: H01L49/02 ,  H01L23/48 ,  H01L23/522

    Abstract: A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate. The 3D inductor also includes a first trace on a first surface of the substrate, coupled to a first end of the first plurality of micro-TSVs. The 3D inductor further includes a second trace on a second surface of the substrate, opposite the first surface, coupled to a second end, opposite the first end, of the first plurality of micro-TSVs.

    SURFACE ACOUSTIC WAVE (SAW) DEVICES WITH A DIAMOND BRIDGE ENCLOSED WAVE PROPAGATION CAVITY
    50.
    发明申请
    SURFACE ACOUSTIC WAVE (SAW) DEVICES WITH A DIAMOND BRIDGE ENCLOSED WAVE PROPAGATION CAVITY 审中-公开

    公开(公告)号：WO2022159255A1

    公开(公告)日：2022-07-28

    申请号：PCT/US2021/072641

    申请日：2021-11-30

    Applicant: QUALCOMM INCORPORATED

    Inventor： DUTTA, Ranadeep ,  KIM, Jonghae ,  LAN, Je-Hsiung

    IPC: H03H9/10 ,  H03H9/02 ,  H03H3/10

    Abstract: A surface acoustic wave, SAW, device (200) includes a first interdigital transducer, IDT, (202) and a second IDT (204) each including interdigital electrodes disposed on a first surface of a substrate (212) of piezoelectric material. The SAW device includes a diamond bridge (208) enclosing an air cavity (220) over a wave propagation region on the first surface of the substrate between the first ad second IDTs. The diamond bridge has a reduced height and provides improved thermal conductivity to avoid a reduction in performance and/or life span caused by heat generated in the SAW device. Also disclosed is a process of fabricating a SAW device includes forming the first IDT and the second IDT in a metal layer on a first surface of a substrate comprising a piezoelectric material, the first IDT and the second IDT disposed in a wave propagation region of the first surface of the substrate, and forming a diamond bridge disposed above the wave propagation region.

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