公开(公告)号：DE69328342T2

公开(公告)日：2000-09-07

申请号：DE69328342

申请日：1993-12-09

Applicant: SONY CORP

Inventor： HAYASHI YUTAKA ,  MATSUSHITA TAKESHI

IPC: G11C11/405 ,  G11C11/404 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/786 ,  G11C11/40

Abstract: A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor (TR1) comprising a first semiconductor channel forming region (Ch1), first and second conductive regions (SC1, SC2) and a first conductive gate (G1); and a switching transistor (TR2) comprising a second semiconductor channel forming region (Ch2), third and fourth conductive regions (SC3, SC4) and a second conductive gate (G2); wherein said first conductive gate (G1) and said second conductive gate (G2) are connected to a first memory-cell-selection line (1ST LINE), said fourth conductive region (SC4) is connected to said first semiconductor channel forming region (Ch1), said third conductive region (SC3) is connected to a second memory-cell-selection line (2ND LINE), and said first conductive region (SC1) is connected to a read line (READ LINE).

公开(公告)号：SG74107A1

公开(公告)日：2000-07-18

申请号：SG1998005869

申请日：1998-12-21

Applicant: SONY CORP

Inventor： MATSUSHITA TAKESHI ,  KUSUNOKI MISAO ,  TATSUMI TAKAAKI

IPC: H01L21/316 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L27/12 ,  H01L31/18 ,  H01L21/306 ,  H01L21/321 ,  H01L21/322 ,  H01L21/786 ,  C23C26/00 ,  C25D11/02

Abstract: A semiconductor substrate, a thin film semiconductor device, a manufacturing method thereof and an anodizing apparatus which can reduce the manufacturing cost and save the resources are provided. According to this invention, a semiconductor thin film is formed through a separation layer of a porous semiconductor on a substrate body of sapphire; the semiconductor thin film is separated from the porosity layer and used for a thin film semiconductor device; and the substrate body from which the semiconductor thin film is separated is used again after the separation layer attached thereto is removed by etching. Since sapphire has high strength, high rigidity, high resistance to wearing, high heat resistance, high abrasion resistance and high chemicals resistance, no deterioration and no damage occur even when the substrate body is repetitively used. Thus, the recycle frequency can be increased, and the reduction of the manufacturing cost and the saving of the resources can be promoted.

公开(公告)号：DE69226687T2

公开(公告)日：1999-04-15

申请号：DE69226687

申请日：1992-10-13

Applicant: SONY CORP

Inventor： OCHIAI AKIHIKO ,  HASHIMOTO MAKOTO ,  MATSUSHITA TAKESHI ,  YAMAGISHI MACHIO ,  SATO HIROSHI ,  SHIMANOE MUNEHARU

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8247 ,  H01L21/84 ,  H01L21/76

Abstract: The present invention concerns a method of manufacturing a SOI substrate of forming a thin film of a silicon layer on an insulator substrate by bonding a substrate, wherein the method comprises successively: a step of forming an etching stopping layer on the surface of a silicon substrate, a step of forming an epitaxially grown silicon layer on said etching stopping layer, a step of bonding said silicon substrate formed with said silicon layer with another substrate as the insulator substrate, a step of grinding said silicon substrate from the rear face and etching it till said etching stopping layer is exposed and a step of removing said etching stopping layer.

公开(公告)号：GB2254487B

公开(公告)日：1995-06-21

申请号：GB9206123

申请日：1992-03-20

Applicant: SONY CORP

Inventor： HASHIMOTO MAKOTO ,  MIYAZAWA YOSHIHIRO ,  MATSUSHITA TAKESHI

IPC: H01L27/11

Abstract: A method for manufacture of a full CMOS type SRAM, comprising the steps of forming a first mask layer on a semiconductor layer, and patterning the first mask layer by photolithography to form semiconductor island layers where a driver MOS transistor and a load MOS transistor are formable with a slight space therebetween; forming a second mask layer on the semiconductor layer, and patterning the second mask layer by photolithography in such a manner as to overlap the region with one of the driver and load MOS transistors, but not to overlap the isolating region between the transistors; masking, with a resist film, the region with the other of the driver and load MOS transistors, and etching the first mask layer while masking the same with the resist film and the second mask layer; and etching the semiconductor layer while masking the same with the first mask layer, thereby forming mutually isolated semiconductor island layers where the driver and load MOS transistors are formed respectively. According to this method, the width of each transistor and the space between the transistors can be minimized to consequently achieve an enhanced integration density.

公开(公告)号：DE68920365D1

公开(公告)日：1995-02-16

申请号：DE68920365

申请日：1989-06-16

Applicant: MITSUBISHI MATERIAL SILICON ,  SONY CORP

Inventor： SAITO YUICHI ,  SAKAI SHINSUKE ,  HAYASHI HISAO ,  MATSUSHITA TAKESHI

IPC: B24B37/04 ,  H01L21/306 ,  B24B9/06

Abstract: The present invention relates to a method for polishing a silicon wafer. The method comprises the steps of: (a) supplying a polishing fluid to a polishing surface, the polishing fluid including an alkaline fluid and polishing particles of high-purity silica dispersed in the alkaline fluid, the polishing surface being planar; (b) bringing a silicon wafer in contact with the polishing surface; and (c) moving at least one of the silicon wafer and the polishing surface relative to the other, thereby polishing the silicon wafer. The method is characterized by the following: the polishing surface is made of a ceramic material harder than the silicon wafer and more resistant to mechanochemical polishing than silicon, and the maximum roughness of the ceramic is less than 0.02 mu m.

公开(公告)号：CA1136773A

公开(公告)日：1982-11-30

申请号：CA333370

申请日：1979-08-08

Applicant: SONY CORP

Inventor： OHUCHI NORIKAZU ,  YAMOTO HISAYOSHI ,  HAYASHI HISAO ,  MATSUSHITA TAKESHI

IPC: H01L21/205 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/72 ,  H01L29/737 ,  H01L29/74 ,  H01L31/0368 ,  H01L31/0745 ,  H01L33/00 ,  H01L29/02

Abstract: A hetero-junction bipolar transistor or gate controlled switch which is formed generally of a semiconductor substrate, a first region of first conductivity type in the substrate, a second region of second conductivity type in the substrate and adjacent to the first region, a third region of the first conductivity type adjacent to the second region having at least a portion on the substrate which is comprised of the same element as the substrate and oxygen, the band gap energy of the portion being larger than that of the second region there being transportation of majority carriers in the first region to the third region; wherein the device provides high current gain, superior switching characteristics, the concentration of current is prevented and wherein a method of forming an emitter having a low resistivity is provided.

公开(公告)号：CA1071772A

公开(公告)日：1980-02-12

申请号：CA250473

申请日：1976-04-20

Applicant: SONY CORP

Inventor： AOKI TERUAKI ,  MATSUSHITA TAKESHI ,  MIFUNE TADAYOSHI ,  HAYASHI HISAO

IPC: H01L27/04 ,  H01L21/00 ,  H01L21/265 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/329 ,  H01L21/331 ,  H01L21/76 ,  H01L21/822 ,  H01L23/29 ,  H01L23/31 ,  H01L29/73 ,  H01L29/78 ,  H01L29/8605 ,  H01L21/18

Abstract: An oxygen or nitrogen ion beam is implanted into a polycrystalline silicon or in an amorphous silicon layer, or a single crystal device body or layer, on a semiconductor substrate to an extent sufficient to convert the polycrystalline silicon layer, the amorphous layer or the single crystal device body or layer into a semi-insulating layer having a resistivity of 107 to 1011 ohm-cm, which has improved passivation property.

公开(公告)号：CH608653A5

公开(公告)日：1979-01-15

申请号：CH1371375

申请日：1975-10-23

Applicant: SONY CORP

Inventor： MATSUSHITA TAKESHI ,  HAYASHI HISAO ,  AOKI TERUAKI ,  MOCHIZUKI HIDENOBU

IPC: H01L21/322 ,  H01L21/314 ,  H01L21/331 ,  H01L21/8247 ,  H01L23/31 ,  H01L29/06 ,  H01L29/73 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861 ,  H01L29/02

Abstract: A semiconductive device is provided which includes a single crystal substrate. A first insulating layer arranged on one surface of the substrate is of polycrystalline silicon containing oxygen. A second insulating layer formed on the first insulating layer is of polycrystalline silicon containing one of a group consisting of nitrogen, Si3N4, Al2O3 and silicone resin. The substrate includes at least one PN junction which extends to the said surface of the substrate. A novel method of making is also disclosed.

公开(公告)号：CA1029475A

公开(公告)日：1978-04-11

申请号：CA223550

申请日：1975-04-01

Applicant: SONY CORP

Inventor： MATSUSHITA TAKESHI ,  HAYASHI HISAO ,  AOKI TERUAKI ,  YAMOTO HISAYOSHI ,  KAWANA YOSHIYUKI

IPC: H01L29/73 ,  G02B6/12 ,  H01L21/283 ,  H01L21/314 ,  H01L21/331 ,  H01L21/76 ,  H01L27/04 ,  H01L29/78 ,  H01L29/861

Abstract: 1496814 Semiconductor device passivation SONY CORP 20 March 1975 [30 March 1974] 11691/75 Heading H1K The surface of a semiconductor substrate is passivated by a polycrystalline silicon layer containing from 2 to 45 atomic per cent oxygen. The layer may be applied to the PN junction of a rectifying diode but as described is applied to at least the guard ring protected collector junction of a diffused planar silicon transistor formed in an N type substrate or an N epitaxial layer on an N + substrate. In manufacture the oxide masking used in the diffusion steps is removed and the polycrystalline layer deposited from a mixture of silane and nitrous oxide in a flow of nitrogen with the substrate at 600- 750‹ C., and overcoated with vapour grown silicon dioxide optionally separated from the ploysilicon by a moisture resistant layer, e.g. of aluminium. If silicon tetrachloride is used instead of silane a temperature of 1100‹ C is necessary. Alternative sources of oxygen are NO 2 , NO, O 2 and H 2 O vapour. The oxygen is present as a mixture of silicon monoxide and dioxide at the grain boundaries but is also dispersed in the grains themselves, the dispersion being removed by annealing, e.g. at 1100‹C for 30 minutes. The mean grain size is preferably from 100-1000 Š, and all the grains preferably have sizes within this range. Although the collector breakdown voltage falls with increasing oxygen content the leakage current decreases and if the emitter junction is also covered the amplification factor increases but remains stable.

公开(公告)号：AU8599175A

公开(公告)日：1977-04-28

申请号：AU8599175

申请日：1975-10-24

Applicant: SONY CORP

Inventor： MATSUSHITA TAKESHI ,  HAYASHI HISAO ,  AOKI TERUAKI ,  MOCHIZUKI HIDENOBU

IPC: H01L21/322 ,  H01L21/314 ,  H01L21/331 ,  H01L21/8247 ,  H01L23/31 ,  H01L29/06 ,  H01L29/73 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861 ,  H01L29/12 ,  H01L29/76 ,  H01L27/00

Abstract: A semiconductive device is provided which includes a single crystal substrate. A first insulating layer arranged on one surface of the substrate is of polycrystalline silicon containing oxygen. A second insulating layer formed on the first insulating layer is of polycrystalline silicon containing one of a group consisting of nitrogen, Si3N4, Al2O3 and silicone resin. The substrate includes at least one PN junction which extends to the said surface of the substrate. A novel method of making is also disclosed.