公开(公告)号：FR2839829A1

公开(公告)日：2003-11-21

申请号：FR0205879

申请日：2002-05-14

Applicant: ST MICROELECTRONICS SA

Inventor： TARDIEU OLIVIER ,  MOREAUX CHRISTOPHE ,  KARI AHMED

IPC: H03K19/094 ,  H03K19/12

Abstract: A buffer of reduced size includes a logic gate to raise the potential level of input digital data having a first logic level to a potential equal to a low power supply potential, and to produce intermediate data if a validation signal is active. The buffer also includes a tristate inverter to produce output data, at an output, that are logically inverse to the intermediate data if the validation signal is active and having its output at high impedance if otherwise. Such a buffer is particularly useful as an output buffer for contact cards using a power supply potential different from a potential powering a reader with which the card communicates.

公开(公告)号：DE60000055D1

公开(公告)日：2002-02-28

申请号：DE60000055

申请日：2000-09-11

Applicant: ST MICROELECTRONICS SA

Inventor： MOREAUX CHRISTOPHE

IPC: G06K19/07 ,  G11C7/00

Abstract: The printed integrated circuit has an input circuit (200) and a write accessible memory (140). Binary signals (SA) are transmitted by direct contact between the card and reader (150). A write command (WR) is produced. The input circuit has a control circuit (220) receiving the binary signal and outputting a validation signal (VAL) which activates a write inhibition circuit (240) when the validation signal is inactive.

公开(公告)号：FR2799026B1

公开(公告)日：2001-11-30

申请号：FR9912327

申请日：1999-09-28

Applicant: ST MICROELECTRONICS SA

Inventor： MOREAUX CHRISTOPHE

IPC: G06K19/07 ,  G11C7/00 ,  G06K19/073 ,  G06K7/00 ,  H03K5/153

Abstract: The printed integrated circuit has an input circuit (200) and a write accessible memory (140). Binary signals (SA) are transmitted by direct contact between the card and reader (150). A write command (WR) is produced. The input circuit has a control circuit (220) receiving the binary signal and outputting a validation signal (VAL) which activates a write inhibition circuit (240) when the validation signal is inactive.

公开(公告)号：FR2787912B1

公开(公告)日：2001-03-02

申请号：FR9816367

申请日：1998-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： MOREAUX CHRISTOPHE

IPC: H01L27/118 ,  H03K19/173 ,  G11C17/14 ,  H03H3/00 ,  H03H11/00

Abstract: A configurable electronic circuit having configuration nodes is provided. Each of the configuration nodes is coupled to corresponding first circuitry that is non-modifiable during configuration and second circuitry that is modifiable during the configuration. The non-modifiable first circuitry selectively imposes one of at least a first potential and a second potential on the configuration node prior to configuration, and the modifiable second circuitry allows modification of the potential imposed on the configuration node by the non-modifiable first circuitry. In a preferred embodiment, the modifiable second circuitry includes at least one fuse that is in an intact state before configuration and that can be changed to a destroyed state after configuration. This enables a reduction in the number of fuses that have to be destroyed during the configuration of the circuit. Also provided is an information processing system that includes at least one configurable electronic circuit having configuration nodes.

公开(公告)号：DE69900032D1

公开(公告)日：2000-12-28

申请号：DE69900032

申请日：1999-05-26

Applicant: ST MICROELECTRONICS SA

Inventor： MOREAUX CHRISTOPHE ,  LECONTE BRUNO

IPC: G11C7/10 ,  G11C7/00

Abstract: The integrated circuit (1) comprises two memory units (MEM1,MEM2) connected to an input/output (E/S) bus (2), external and internal address buses (3,4). A redirection circuit and the first memory unit are configurable according to two formats with inputs of a selection signal (Sel). The first memory unit, which is configurable according to two different formats, is of much higher capacity than the second memory unit of a fixed format, e.g. 16 bits and 8 bits formats. A variant of the device comprises inputs of two selection signals to the memory units and to the redirection circuit, or two redirection circuits with separate inputs of the selection signals. The redirection circuit contains one or two multiplexers controlled by the selection signal, or four multiplexers and two ports for the input of two selection signals.