公开(公告)号：DE69413793T2

公开(公告)日：1999-04-15

申请号：DE69413793

申请日：1994-01-21

Applicant: ST MICROELECTRONICS SRL

Inventor： MACCARRONE MARCO ,  OLIVO MARCO ,  GOLLA CARLA MARIA

IPC: G11C17/00 ,  G05F3/24 ,  G05F3/26 ,  H03F1/30

Abstract: A current source (20) including a current mirror circuit (1) and an active load circuit (7-9) which form a reference branch, for setting a reference current value (Ir), and a mirroring branch, defining an output current value, connected between supply (30) and ground. A voltage stabilizing transistor (22) is interposed between the current mirror circuit (1) and the load circuit (7-9) in the reference branch only, and is so biased as to maintain its gate terminal (23) at a predetermined voltage. As such, the potential with respect to ground of the drain terminal of the reference branch load transistor (7) is fixed, so that its drain-source voltage drop (and the current through it) is substantially independent of supply voltage. The current source (20) may be used to advantage in an oscillator for generating the clock signal of a nonvolatile memory.

公开(公告)号：DE69413793D1

公开(公告)日：1998-11-12

申请号：DE69413793

申请日：1994-01-21

Applicant: ST MICROELECTRONICS SRL

Inventor： MACCARRONE MARCO ,  OLIVO MARCO ,  GOLLA CARLA MARIA

IPC: G11C17/00 ,  G05F3/24 ,  G05F3/26 ,  H03F1/30

Abstract: A current source (20) including a current mirror circuit (1) and an active load circuit (7-9) which form a reference branch, for setting a reference current value (Ir), and a mirroring branch, defining an output current value, connected between supply (30) and ground. A voltage stabilizing transistor (22) is interposed between the current mirror circuit (1) and the load circuit (7-9) in the reference branch only, and is so biased as to maintain its gate terminal (23) at a predetermined voltage. As such, the potential with respect to ground of the drain terminal of the reference branch load transistor (7) is fixed, so that its drain-source voltage drop (and the current through it) is substantially independent of supply voltage. The current source (20) may be used to advantage in an oscillator for generating the clock signal of a nonvolatile memory.

公开(公告)号：DE69411532D1

公开(公告)日：1998-08-13

申请号：DE69411532

申请日：1994-02-17

Applicant: ST MICROELECTRONICS SRL

Inventor： GOLLA CARLA MARIA ,  MACCARRONE MARCO

IPC: G11C29/00 ,  G11C29/04 ,  G06F11/20

Abstract: A method for programming non-volatile row redundancy memory registers (RR1-RR4) each one associated to a respective pair of redundancy row and each one programmable to store in two subsets (1,2;1,2') of a set of memory cells (MC0-MC9) a pair of addresses of a respective pair of adjacent defective rows; each memory register is supplied with row address signals (R0-R9) and with a respective selection signal (C0-C3) belonging to a set of column address signals (CABUS); the method provides for: applying to the row address signals (R0-R9) the address of a first defective row of the pair of adjacent defective rows; activating one of the selection signals (C0-C3) for selecting the memory register which is to be programmed; applying to a further column address signal (C4) a first logic level to select for programming, in the selected memory register, a first subset (1,2) of memory cells (MC0-MC9); enabling the programming of the address of the first defective row of the pair of adjacent defective rows into the first subset (1,2) of memory cells; applying to at least a subset (R0-R3) of the row address signals (R0-R9) the address of the second defective row of the pair; applying to the further column address signal (C4) a second, opposite logic level to select for programming, in the selected memory register (RR1-RR4), at least a group (2') of memory cells (MC0-MC3) of the second subset (1,2') of the two subsets (1,2;1,2') of memory cells; enabling the programming of the address of the second defective row of the pair of adjacent defective rows into the second subset (1,2') of memory cells.