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    TESTING METHOD FOR NONVOLATILE MEMORY
    5.
    发明专利
    TESTING METHOD FOR NONVOLATILE MEMORY 失效

    公开(公告)号：JPH07220500A

    公开(公告)日：1995-08-18

    申请号：JP1166395

    申请日：1995-01-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OLIVO MARCO ,  MACCARRONE MARCO

    IPC: G11C17/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C29/56 ,  G11C16/06

    Abstract: PURPOSE: To execute a test faster by excluding an internal state machine and directly programming a cell matrix to testify that the program is correct. CONSTITUTION: A test circuit 10 receives a test mode active signal from an address bus 2 and a data bus 3, the positions of switches I1 to 3 are switched. The switch I1 is switched to a second circuit 8 (programming circuit) connecting a signal WEN to a memory matrix. The switch I2 is switched to a first circuit 6 (generator) connecting a signal CEN to a circuit 2 and a word line. The switch 3 directly input a signal OPE to the circuit 6 and an output buffer circuit 7. As the result of this, the internal state machine is excluded and addresses can freely be used. Then a new test method programming a desired cell through the use of a control signal with a new meaning and testifying that the program is correct is obtained.

    READ TIMING METHOD OF NONVOLATILE MEMORY AND CIRCUIT
    8.
    发明专利
    READ TIMING METHOD OF NONVOLATILE MEMORY AND CIRCUIT 失效

    公开(公告)号：JPH0855485A

    公开(公告)日：1996-02-27

    申请号：JP4796295

    申请日：1995-02-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

    Abstract: PURPOSE: To derive optimum performance from a memory by enabling the circuit with a switching edge, making the circuit programmable, and protecting the circuit against noise. CONSTITUTION: A delay unit 23 inputs a low-level signal, which goes up to a high level a delay time corresponding to the contents of memory elements 20 and 22 after a leading edge of a signal ATD is received, to a NOR gate 27. The gate 27 inputs a signal PC as a signal DET to an asymmetrical delay unit 24 through a NOR gate 28, and a low-level data simulation signal SP is outputted which goes up to the high level a delay time based upon the elements 20 and 21 after a leading edge of the signal DET is received. The signal SP is transferred to an output similar circuit 33 and at its completion time, a high level is outputted. Consequently, signals N and L are switched to the low level and the output STP of a continuance expanding circuit 51 goes down to a low level. Consequently, the data loading is completed. This loading lasts accurately in an output circuit 108 during data propagation.

    VOLTAGE REGULATOR, ITS PROGRAMMING-VOLTAGE SUPPLY METHOD, AND BIAS-CURRENT CORRECTION METHOD AND MEMORY DEVICE
    9.
    发明专利
    VOLTAGE REGULATOR, ITS PROGRAMMING-VOLTAGE SUPPLY METHOD, AND BIAS-CURRENT CORRECTION METHOD AND MEMORY DEVICE 失效

    公开(公告)号：JPH07235194A

    公开(公告)日：1995-09-05

    申请号：JP11995

    申请日：1995-01-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MACCARRONE MARCO ,  OLIVO MARCO ,  GOLLA CARLA ,  PADOAN SILVIA

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

    Abstract: PURPOSE: To improve both stability and reliability by using a current mirror, a resistive divider, an amplifier stage, a source follow-up transistor TR and a resistive path connected to a reference potential. CONSTITUTION: A current mirror 3 corrects the voltage drop that is caused by the serial resistance of a bit line where its programming is ready. Then this programming is carried out by giving the voltage which varies according to the current draw of one or plural cells to be programmed to the reference potential that is obtained from reference voltage VPP via a resistive divider 2. A TR MG2 is prepared to hold a resistive path 8 reaching the ground from the programming voltage VP, and the bias current is partly subtracted from an inverted current. This subtraction part is decided by the W/L ratio of a TR contained in the mirror 3. As a result, any offset voltage that is generated on a programming line can be corrected.

    Electrostatic discharge protective network
    10.
    发明专利
    Electrostatic discharge protective network 审中-公开
    静电放电保护网络

    公开(公告)号：JPH11274319A

    公开(公告)日：1999-10-08

    申请号：JP37471898

    申请日：1998-12-28

    Applicant: St Microelectronics Srl ,  エスティマイクロエレクトロニクス・ソチエタ・ア・レスポンサビリタ・リミタータ

    Inventor： COLOMBO PAOLO ,  MULATTI JACOPO ,  CAMPARDO GIOVANNI ,  MACCARRONE MARCO ,  ANNUNZIATA ROBERTO

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

    CPC classification number: H01L27/0259 ,  H01L27/0251

    Abstract: PROBLEM TO BE SOLVED: To provide an electrostatic discharge(ESD) protective network, which has such structural and functional features that meet the nonsensitive requirements of a substrate for noise and accordingly, can isolate various circuit blocks from noise or disturbance. SOLUTION: An ESD protective network incorporates first ESD protective parts 14 for the input stage of a circuit structure, second ESD protective parts 5 for the output stage of the circuit structure, at least one ESD protective parts B0 between a primary power source Vcc and a primary ground GND, and at least one EDGE protective parts B between a secondary power source Vcc- IO and a secondary ground GND- IO, and the first and second protective parts 15 and 5 commonly use the input-output terminal 20 of an integrated circuit structure.

    Abstract translation: 要解决的问题：提供一种静电放电（ESD）保护网络，其具有满足基板对噪声的不敏感要求的结构和功能特征，因此可以将各种电路块与噪声或干扰隔离开来。 解决方案：ESD保护网络包括用于电路结构的输入级的第一ESD保护部件14，用于电路结构的输出级的第二ESD保护部件5，主电源Vcc和 主接地GND以及次级电源Vcc-IO和次级地GND-IO之间的至少一个EDGE保护部分B，并且第一和第二保护部分15和5通常使用集成电路的输入 - 输出端子20 结构体。

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