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    GENERATING METHOD OF LOAD SIGNAL TO NONVOLATILE MEMORY AND CIRCUIT THEREOF
    3.
    发明专利
    GENERATING METHOD OF LOAD SIGNAL TO NONVOLATILE MEMORY AND CIRCUIT THEREOF 失效

    公开(公告)号：JPH0863953A

    公开(公告)日：1996-03-08

    申请号：JP4930295

    申请日：1995-02-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA

    IPC: G11C17/00 ,  G11C5/14 ,  G11C7/00 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

    Abstract: PURPOSE: To obtain a load signal generating method and circuit for a non- volatile memory. CONSTITUTION: A circuit 1 is used to generate a variable length data load pulse L depending on the requirement and is provided with a source 5 for applying a short load signal SP and a delay element 19 for generating a long pulse STP when the short load signal appears. Static operation mode is given so that a load pulse is generated continuously through the static operation so long as the critical state (standby condition, low voltage) is continued. An expanded pulse is always generated when the static operation mode terminates, while a delay element 19 is disabled by a command EN when the expanded timing is not required.

    READ TIMING METHOD OF NONVOLATILE MEMORY AND CIRCUIT
    5.
    发明专利
    READ TIMING METHOD OF NONVOLATILE MEMORY AND CIRCUIT 失效

    公开(公告)号：JPH0855485A

    公开(公告)日：1996-02-27

    申请号：JP4796295

    申请日：1995-02-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

    Abstract: PURPOSE: To derive optimum performance from a memory by enabling the circuit with a switching edge, making the circuit programmable, and protecting the circuit against noise. CONSTITUTION: A delay unit 23 inputs a low-level signal, which goes up to a high level a delay time corresponding to the contents of memory elements 20 and 22 after a leading edge of a signal ATD is received, to a NOR gate 27. The gate 27 inputs a signal PC as a signal DET to an asymmetrical delay unit 24 through a NOR gate 28, and a low-level data simulation signal SP is outputted which goes up to the high level a delay time based upon the elements 20 and 21 after a leading edge of the signal DET is received. The signal SP is transferred to an output similar circuit 33 and at its completion time, a high level is outputted. Consequently, signals N and L are switched to the low level and the output STP of a continuance expanding circuit 51 goes down to a low level. Consequently, the data loading is completed. This loading lasts accurately in an output circuit 108 during data propagation.

    READ DEVICE OF MEMORY ARRAY CELL
    6.
    发明专利
    READ DEVICE OF MEMORY ARRAY CELL 失效

    公开(公告)号：JPH0836884A

    公开(公告)日：1996-02-06

    申请号：JP6279395

    申请日：1995-03-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA MARIA ,  OLIVO MARCO ,  PADOAN SILVIA

    IPC: G11C11/409 ,  G11C7/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28

    Abstract: PURPOSE: To provide equal current paths with a compact structure, and exhibit the possibility of switching one or more current paths. CONSTITUTION: A current path of an array branch 21 is constituted of a load transistor 27, and current paths 32a, 33a of a reference branch 22 are constituted of load transistors 32, 33. The load transistor 32 is connected with a diode, and the load transistor 33 is switchable by a switching network (35-50) connected to a gate terminal of the load transistor 33.

    ROW-ADDRESS DECODING AND SELECTION CIRCUIT
    7.
    发明专利
    ROW-ADDRESS DECODING AND SELECTION CIRCUIT 失效

    公开(公告)号：JPH07201193A

    公开(公告)日：1995-08-04

    申请号：JP31188894

    申请日：1994-12-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA MARIA ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C8/12 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04

    Abstract: PURPOSE: To provide a two rows address decoding/selection circuit for a non- volatile memory device, which has redundancy, which can electrically be deleted and into which data can be written. CONSTITUTION: Circuit blocks PGO-PG15 generate carry-out signals CO0-C015 which are supplied to the carry-in terminals CI0-C115 of a circuit block in a next stage and are activated when selection signals PO-P15 are activated. The first circuit block PG0 has has the carry-in terminal CI0 connected to reference potential GND. The circuit blocks PG0-PG15 supply control signals E activated by the control circuit 6 of the memory device when defective rows WL0-WL15 are addressed in prior to the electrical deletion of the memory device during a preprogramming operation. When carry-out signals CO-C015 are activated, the selection signals PO-P15 are activated and the two adjacent rows WL0-WL15 can be selected.

    OUTPUT CIRCUIT FOR INTEGRATED CIRCUIT
    8.
    发明专利
    OUTPUT CIRCUIT FOR INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH11195715A

    公开(公告)日：1999-07-21

    申请号：JP29938198

    申请日：1998-10-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MULATTI JACOPO ,  ZANARDI STEFANO ,  GOLLA CARLA MARIA ,  CONCI ARMANDO

    IPC: H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0175

    Abstract: PROBLEM TO BE SOLVED: To reduce the effects of noise exerted to an input stage and internal circuit of an integrated circuit by an output stage of the integrated circuit. SOLUTION: An output stage for an integrated circuit is provided with a first transistor means P2 and a second transistor means N2, serially connected between a first external voltage Vcc and a second external voltage Gnd on the outside of the integrated circuit 100 respectively, through a first and a second electric connection means L2 and L4. The first transistor means P2 transmits the first external voltage Vcc to an output line 5 of the integrated circuit, and the second transistor means N2 transmits the second external voltage Gnd to the output line 5 of the integrated circuit. The second transistor means N2 is formed inside a first well 130 of a first conductivity type provided inside a second well 140 of a second conductivity type formed inside a substrate 7 of the first conductivity type. The second well 140 of the second conductive type is connected through a third electric connection means L21 which is different from the first electric connection means L2 to the first external voltage Vcc.

    INTERNAL TIMING METHOD TO REWRITABLE MEMORY AND CIRCUIT THEREOF
    10.
    发明专利
    INTERNAL TIMING METHOD TO REWRITABLE MEMORY AND CIRCUIT THEREOF 失效

    公开(公告)号：JPH0896569A

    公开(公告)日：1996-04-12

    申请号：JP5038495

    申请日：1995-02-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO ,  GOLLA CARLA MARIA

    IPC: G11C17/00 ,  G11C7/00 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

    Abstract: PURPOSE: To obtain an internal timing method to a rewritable memory and a circuit thereof. CONSTITUTION: A circuit 1 generates slow or fast overall timing configuration and flexible timing enabling the two configuration of pre-charge and detection intervals by giving the levels of two short and long periods. For conduct the generation of the timing, variable asymmetric propagation lines 5, 37 consisting of a series of basic delay elements 6-8, 38, 40 bringing data to an enable or disenable state on the basis of logical signals TIMS, PCS, and DETS stored are contained in the circuit 1, and the state is determined when a memory 100 executed by the circuit is debugged.

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