公开(公告)号：JP2737686B2

公开(公告)日：1998-04-08

申请号：JP5377795

申请日：1995-02-20

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

IPC: G11C11/413 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32 ,  G11C17/00

公开(公告)号：JPH07200339A

公开(公告)日：1995-08-04

申请号：JP29700494

申请日：1994-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： MACCARRONE MARCO ,  OLIVO MARCO

IPC: G01R31/28 ,  G01R31/3185 ,  G06F7/00 ,  G06F11/22 ,  G11C29/48

Abstract: PURPOSE: To provide a circuit constitution and its method which can facilitate a PLA(programmable logic array) test with higher safety and at a higher speed. CONSTITUTION: A circuit constitution 1 which tests a matrix 2 is provided with a series of input latches 7 and output latches 8 which are connected to the matrix 2, and at least a test data bus 11 and a test address bus 12 which are connected to the latches 7 and 8. In such a constitution, the matrix test time is considerably shortened.

公开(公告)号：JPH11260097A

公开(公告)日：1999-09-24

申请号：JP36334998

申请日：1998-12-21

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO ,  MAURELLI ALFONSO ,  OLIVO MARCO

IPC: G11C16/06 ,  G06F11/10 ,  G11C29/00 ,  G11C29/06 ,  G11C29/52

Abstract: PROBLEM TO BE SOLVED: To provide a method for self-testing and correcting an error caused by the charge loss of a flash memory. SOLUTION: Read and parity check are repeated sequentially per byte and integrity is verified for values stored in respective parity bits of a parity value. It the verification is negative, and parity verification is continued sequentially starting from the first row until a row generating a negative verification result is identified while sustaining the current row address. If a discrete tail bit is '1', it is rewritten to '0'.

公开(公告)号：JP2682502B2

公开(公告)日：1997-11-26

申请号：JP5377695

申请日：1995-02-20

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  MACCARRONE MARCO ,  OLIVO MARCO

IPC: G11C17/00 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32

公开(公告)号：JPH0822698A

公开(公告)日：1996-01-23

申请号：JP2664295

申请日：1995-02-15

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

Abstract: PURPOSE: To eliminate the need of generating an ON-CHIP exclusive signal to reduce the chip size by using the existing signal line in a memory to program a redundant register. CONSTITUTION: A two-dimensional array memory matrix provided with a 16-bit data bus is divided into a plurality of portions each of which is composed of a plurality of bit groups. Redundant registers RR1-4 composed of programmable non-volatile memory is capable of programming an address of the defective bit line received from a column address signal CABUS in its first block 1. Moreover, in the second block 2, an identification code MCS7-10 of the bit group to which a defective bit line belongs obtained from the first part R1-4 of the row address signal set RABUS. A programming selection means 6 selects the redundant register RR1-4 with the second part R5-8 of the row address signal set RABUS to store the address information of the defective bit line.

公开(公告)号：JPH07220500A

公开(公告)日：1995-08-18

申请号：JP1166395

申请日：1995-01-27

Applicant: ST MICROELECTRONICS SRL

Inventor： OLIVO MARCO ,  MACCARRONE MARCO

IPC: G11C17/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C29/56 ,  G11C16/06

Abstract: PURPOSE: To execute a test faster by excluding an internal state machine and directly programming a cell matrix to testify that the program is correct. CONSTITUTION: A test circuit 10 receives a test mode active signal from an address bus 2 and a data bus 3, the positions of switches I1 to 3 are switched. The switch I1 is switched to a second circuit 8 (programming circuit) connecting a signal WEN to a memory matrix. The switch I2 is switched to a first circuit 6 (generator) connecting a signal CEN to a circuit 2 and a word line. The switch 3 directly input a signal OPE to the circuit 6 and an output buffer circuit 7. As the result of this, the internal state machine is excluded and addresses can freely be used. Then a new test method programming a desired cell through the use of a control signal with a new meaning and testifying that the program is correct is obtained.

公开(公告)号：JP2674550B2

公开(公告)日：1997-11-12

申请号：JP4796295

申请日：1995-02-14

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

IPC: G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

公开(公告)号：JPH0855485A

公开(公告)日：1996-02-27

申请号：JP4796295

申请日：1995-02-14

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

IPC: G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

Abstract: PURPOSE: To derive optimum performance from a memory by enabling the circuit with a switching edge, making the circuit programmable, and protecting the circuit against noise. CONSTITUTION: A delay unit 23 inputs a low-level signal, which goes up to a high level a delay time corresponding to the contents of memory elements 20 and 22 after a leading edge of a signal ATD is received, to a NOR gate 27. The gate 27 inputs a signal PC as a signal DET to an asymmetrical delay unit 24 through a NOR gate 28, and a low-level data simulation signal SP is outputted which goes up to the high level a delay time based upon the elements 20 and 21 after a leading edge of the signal DET is received. The signal SP is transferred to an output similar circuit 33 and at its completion time, a high level is outputted. Consequently, signals N and L are switched to the low level and the output STP of a continuance expanding circuit 51 goes down to a low level. Consequently, the data loading is completed. This loading lasts accurately in an output circuit 108 during data propagation.

公开(公告)号：JPH0836884A

公开(公告)日：1996-02-06

申请号：JP6279395

申请日：1995-03-22

Applicant: ST MICROELECTRONICS SRL

Inventor： GOLLA CARLA MARIA ,  OLIVO MARCO ,  PADOAN SILVIA

IPC: G11C11/409 ,  G11C7/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28

Abstract: PURPOSE: To provide equal current paths with a compact structure, and exhibit the possibility of switching one or more current paths. CONSTITUTION: A current path of an array branch 21 is constituted of a load transistor 27, and current paths 32a, 33a of a reference branch 22 are constituted of load transistors 32, 33. The load transistor 32 is connected with a diode, and the load transistor 33 is switchable by a switching network (35-50) connected to a gate terminal of the load transistor 33.

公开(公告)号：JPH07235194A

公开(公告)日：1995-09-05

申请号：JP11995

申请日：1995-01-04

Applicant: ST MICROELECTRONICS SRL

Inventor： MACCARRONE MARCO ,  OLIVO MARCO ,  GOLLA CARLA ,  PADOAN SILVIA

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

Abstract: PURPOSE: To improve both stability and reliability by using a current mirror, a resistive divider, an amplifier stage, a source follow-up transistor TR and a resistive path connected to a reference potential. CONSTITUTION: A current mirror 3 corrects the voltage drop that is caused by the serial resistance of a bit line where its programming is ready. Then this programming is carried out by giving the voltage which varies according to the current draw of one or plural cells to be programmed to the reference potential that is obtained from reference voltage VPP via a resistive divider 2. A TR MG2 is prepared to hold a resistive path 8 reaching the ground from the programming voltage VP, and the bias current is partly subtracted from an inverted current. This subtraction part is decided by the W/L ratio of a TR contained in the mirror 3. As a result, any offset voltage that is generated on a programming line can be corrected.