中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

112 records (took 0.034 seconds)

    42.
    发明专利
    未知

    公开(公告)号：IT8883645D0

    公开(公告)日：1988-06-28

    申请号：IT8364588

    申请日：1988-06-28

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： OLIVO MARCO ,  PASCUCCI LUIGI ,  VILLA CORRADO

    IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07

    Abstract: A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.

    43.
    发明专利
    未知

    公开(公告)号：DE69412230T2

    公开(公告)日：1999-04-08

    申请号：DE69412230

    申请日：1994-02-17

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

    Abstract: A method for programming redundancy registers in a column redundancy integrated circuitry for a semiconductor memory device with columns of memory elements grouped together to form portions of a bidimensional array of memory elements, the column redundancy circuitry comprising at least one plurality of non-volatile memory registers (RR1-RR4) each one associated to a respective redundancy column of redundancy memory elements and each one programmable to store an address of a defective column and an identifying code (MCS7-MCS10) for identifying the portion of the bidimensional array to which the defective column belongs, provides for supplying each non-volatile memory register (RR1-RR4) with column address signals (CABUS) and with a first subset (R1-R4) of row address signals (RABUS), which when one of the non-volatile memory registers (RR1-RR4) is to be programmed carry the address of a defective column and said identifying code (MCS7-MCS10) respectively, and for activating one signal of a second subset (R5-R8) of the row address signals (RABUS), supplied to programming selection means (6), for selecting one respective non-volatile memory register (RR1-RR4) of said plurality to cause the data carried by the column address signals (CABUS) and by the first subset (R1-R4) of the row address signals to be programmed into said one respective non-volatile memory register (RR1-RR4).

    45.
    发明专利
    未知

    公开(公告)号：IT1253679B

    公开(公告)日：1995-08-22

    申请号：ITVA910026

    申请日：1991-08-30

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G06F1/24 ,  H03K17/00 ,  H03K17/22 ,  H01L

    Abstract: A power-on reset circuit utilizes capacitive couplings and does not establish any static current path bewteen the supply rails. The circuit has a null static consumption and may be advantageously integrated in CMOS micrologics. Moreover the circuit is insensitive to rebounds on the supply rails and to internal and external noise.

    46.
    发明专利
    未知

    公开(公告)号：DE69109521D1

    公开(公告)日：1995-06-14

    申请号：DE69109521

    申请日：1991-02-07

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: H03K3/354 ,  H02M3/07

    Abstract: A voltage-boosted phase oscillator for driving a voltage multiplier comprises two intermeshed ring oscillators, each composed by an odd number of inverters connected in cascade through a closed loop and generating a normal phase and a voltage-boosted phase derived from the normal phase through a bootstrap circuit. The frequency of oscillation of both intermeshed ring oscillators is established by means of two similar RC networks common to both loops. The synchronization of the respective oscillations of the two rings is ensured by means of a plurality of SR flip-flops connected in cascade, formed by two NAND gates which, singularly, constitute as many inverters of the two rings. The oscillation and the arresting of the oscillation are controlled by means of a logic signal fed to a common input of a first pair of NAND gates which constitute respectively a first inverter of the relative ring oscillator and to a second input of which the phase produced by the relative ring oscillator is fed.

    49.
    发明专利
    未知

    公开(公告)号：IT1246238B

    公开(公告)日：1994-11-17

    申请号：IT8360490

    申请日：1990-02-16

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: H03K3/354 ,  H02M3/07 ,  H03B

    Abstract: A voltage-boosted phase oscillator for driving a voltage multiplier comprises two intermeshed ring oscillators, each composed by an odd number of inverters connected in cascade through a closed loop and generating a normal phase and a voltage-boosted phase derived from the normal phase through a bootstrap circuit. The frequency of oscillation of both intermeshed ring oscillators is established by means of two similar RC networks common to both loops. The synchronization of the respective oscillations of the two rings is ensured by means of a plurality of SR flip-flops connected in cascade, formed by two NAND gates which, singularly, constitute as many inverters of the two rings. The oscillation and the arresting of the oscillation are controlled by means of a logic signal fed to a common input of a first pair of NAND gates which constitute respectively a first inverter of the relative ring oscillator and to a second input of which the phase produced by the relative ring oscillator is fed.

    50.
    发明专利
    未知

    公开(公告)号：DE69012382D1

    公开(公告)日：1994-10-20

    申请号：DE69012382

    申请日：1990-03-12

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： OLIVO MARCO ,  RIVA CARLO

    IPC: G11C17/00 ,  G11C16/04 ,  G11C16/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

    Abstract: A reference cell for reading EEPROM memory devices, capable of discharging any charges present in its own floating gate (3) without varying the geometry of the cell with respect to that of the associated memory cells and without requiring specific manufacturing steps. For this purpose, a switch element, for example a diode (D1), is provided between the floating gate (3) and the substrate (11) of the device and discharges any charges present in the floating gate toward the substrate during the cell idle state (in the absence of read signals)

Patent Agency Ranking