公开(公告)号：EP0788087A1

公开(公告)日：1997-08-06

申请号：EP97101196.0

申请日：1997-01-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Clatanoff, Todd A. ,  Markandey, Vishal ,  Marshall, Stephen W.

IPC: G09G3/34 ,  G09G3/20 ,  H04N9/69

CPC classification number: H04N9/69 ,  G09G3/2007 ,  G09G3/2062 ,  G09G3/34 ,  G09G3/346 ,  G09G2320/0276 ,  H04N5/14 ,  H04N5/202 ,  H04N5/21 ,  H04N19/527 ,  H04N19/86

Abstract: A method and device for producing an accurate approximation of a digital input word translated by a monotonic transfer function. The digital word is translated into a non-monotonic output word comprised of a closest-approximation component and an error component. The error component is zero for regions in which each consecutive input word produces a unique closest-approximation component. In regions in which each consecutive input word produces the same closest-approximation component, the error signal represents the number of consecutive input words which produce the same closest-approximation component, and the position within that run of consecutive input words occupied by the present input word. The approximation is performed by first translating the range of input data words into the closest approximation output words 900, detecting regions in which consecutive output words are the same 902, calculating an accumulated error code for each location 904, and adjusting the closest approximation output words using the accumulated error code 906.

Abstract translation: 一种用于在由单调传递函数转换的数字输入字的准确近似生产方法和设备。 该数字字被转换成由关于误差分量的最近近似组分和非单调输出字。 误差成分为其中每个连续的输入字产生唯一的最近近似部件区域为零。 在其中每个连续输入字产生相同的最近的逼近部件，darstellt的哪个产生相同的最近的逼近部件连续的输入字的数目的误差信号，以及内的位置区并运行的由本输入被占据的连续输入字 字。 该近似通过第一平移的输入数据字转换为所述最接近输出字900的范围内，检测在哪个连续输出字是相同的902区域，计算到累积误差代码对于每个位置904，以及调整所述最近的近似输出字进行 用累积的错误代码906

公开(公告)号：EP0770981A2

公开(公告)日：1997-05-02

申请号：EP96116031.4

申请日：1996-10-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Markandey, Vishal ,  Doherty, Donald B. ,  Gove, Robert J.

IPC: G09G3/34

CPC classification number: G09G3/2007 ,  G09G3/2018 ,  G09G3/2037 ,  G09G3/346 ,  G09G2320/0266 ,  H04N5/7458 ,  H04N2005/7466

Abstract: A method of pulse width modulation using a spatial light modulator (40) with a finite transition time. The method uses m bits per sample to digitize the incoming data, but apportions the LSB times for pulse width modulation based upon m-1 bits. The current video frame displays all of the bits for each sample, except for the LSBs for each sample. The next video frame displays all of the bits for each sample, adding one more LSB for dividing up the frame time. The first frame could use either the additional LSB time and display no data, or it could use only that number of LSB times it needs. In the latter, the system will have to adjust to different partitions of the frame time for alternating frames. The system includes a spatial light modulator (40), a memory (42), a formatter (48), a sequence controller (44) and a toggle circuit (46), to perform this method.

Abstract translation: 一种使用具有有限转换时间的空间光调制器（40）进行脉宽调制的方法。 该方法使用每个采样的m位数字化输入数据，但是基于m-1位将脉冲宽度调制的LSB乘以分配。 当前视频帧显示每个样本的所有位，除了每个样本的LSB。 下一个视频帧显示每个样本的所有位，并添加一个LSB​​以分割帧时间。 第一帧可以使用附加的LSB时间并且不显示任何数据，也可以仅使用它需要的LSB次数。 在后者中，系统将不得不针对交替帧调整帧时间的不同分区。 该系统包括空间光调制器（40），存储器（42），格式化器（48），序列控制器（44）和切换电路（46），以执行该方法。

公开(公告)号：EP0740467A1

公开(公告)日：1996-10-30

申请号：EP96106420.1

申请日：1996-04-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Markandey, Vishal ,  Hewlett, Gregory J.

IPC: H04N5/44 ,  H04N9/31 ,  H04N7/01

CPC classification number: H04N5/74 ,  H04N7/0112 ,  H04N7/012

Abstract: A system (22) and method for converting progressive scan interlaced video data (28) that was originally produced on film to interlaced data. The most recent previous field and the second most recent field are stored in field delays (24 and 26). The most recent previous field is compared to the current field and the second most recent field to generate two motion signals. The field that generates the smallest motion signal when compared to the most recent previous field is then used to perform field insert for that field. The field insert results in progressive frames of data of the image that was produced originally on film. The system (22) also determines whether the film conversion is necessary on whether the data is used for conventional-format progressive scan conversion.

Abstract translation: 具有逐行扫描显示的电视系统具有用于发送原始在电影上制作的数据的当前视频场的输入线。 第一存储器存储最近的先前视频字段的数据，并且第二存储器存储用于第二最前面视频字段的数据。 处理器将最近的先前字段与当前字段和第二最前面的字段进行比较，使得通过比较当前字段和最近的先前字段之间以及最近的先前字段和第二字段之间的运动信号来选择运动信号 最前面的场，其中最小运动信号用于生成最初在胶片上产生的数据的渐进帧。 空间光调制器将视频数据的渐进帧显示为图像。 处理器可操作地设置最小运动信号的最小阈值以减少噪声影响。

公开(公告)号：EP0709822A3

公开(公告)日：1996-07-31

申请号：EP95117187.5

申请日：1995-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gove, Robert J. ,  Abe, Keiichiroh ,  Kamei, Sohichiroh ,  Doherty, Donald B. ,  Markandey, Vishal

IPC: G09G3/34

CPC classification number: G09G3/2092 ,  G06K15/1252 ,  G06K2215/111 ,  G09G3/2022 ,  G09G2310/027 ,  G09G2340/0492 ,  G09G2360/18 ,  H04N1/1903 ,  H04N1/193 ,  H04N1/1934 ,  H04N5/4401 ,  H04N5/7458 ,  H04N7/01 ,  H04N2005/7466

Abstract: A data reformatter/frame memory (112) for efficiently orthogonally reordering a digital data stream. The disclosed reformatter/frame memory (112) is typically used in conjunction with a display device (124) for displaying the digital data, and a display controller (132) for coordinating the transfer of data between the reformatter/frame memory (112) and the display device (124). According to one embodiment, a data reformatter for a video display system includes at least one reformatter memory plane. The memory plane comprises an input bus, an m x n array of memory cells in communication with the input bus, and an m-bit-wide output bus. The array of memory cells receives and stores m n-bit-wide input data words and outputs n m-bit-wide output data words. Each of the m-bit-wide output data words is comprised of one bit from each of the m n-bit-wide input data words.

公开(公告)号：EP0713117A1

公开(公告)日：1996-05-22

申请号：EP95117185.9

申请日：1995-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Smith, Gregory C. ,  Gove, Robert J. ,  Boysel, Robert M. ,  Markandey, Vishal ,  Hornbeck, Larry J.

IPC: G02B26/08

CPC classification number: B81C1/00111 ,  B81B2201/042 ,  B81C2201/014 ,  G02B26/0841 ,  G06K15/1252 ,  G09G3/20 ,  G09G3/2022 ,  G09G2340/0407 ,  G09G2340/0414 ,  G09G2340/0421 ,  G09G2340/0442 ,  G09G2360/02 ,  H04N1/1934 ,  H04N5/4401 ,  H04N5/7458 ,  H04N7/01

Abstract: A support pillar 408 for use with a micromechanical device, particularly a digital micromirror device, comprising a pillar material 404 supported by a substrate 400 and covered with a metal layer 406. The support pillar 408 is fabricated by depositing a layer of pillar material on a substrate 400, patterning the pillar layer to define a support pillar 408, and depositing a metal layer 406 over the support pillar 408 enclosing the support pillar. A planar surface even with the top of the pillar may be created by applying a spacer layer 410 over the pillars 408. After applying the spacer layer 410, holes 414 are patterned into the spacer layer to remove any spacer material that is covering the pillars. The spacer layer is then reflowed to fill the holes and lower the surface of the spacer layer such that the surface is coplanar with the tops of the support pillars 408.

Abstract translation: 用于微机械装置，特别是数字微镜装置的支撑柱408，其包括由衬底400支撑并被金属层406覆盖的支柱材料404.支撑柱408通过将柱材料层沉积在 衬底400，图案化柱层以限定支撑柱408，以及在包围支撑柱的支撑柱408上沉积金属层406。 可以通过在柱408上施加间隔层410来产生甚至具有柱顶部的平面。在施加间隔层410之后，将孔414图案化成间隔层，以移除覆盖柱的任何间隔物材料。 然后将间隔层回流以填充孔并降低间隔层的表面，使得表面与支撑柱408的顶部共面。图像

公开(公告)号：EP0704835A3

公开(公告)日：1996-05-22

申请号：EP95114890.7

申请日：1995-09-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Doherty, Donald B. ,  Pettitt, Gregory ,  Markandey, Vishal

IPC: G09G3/34

CPC classification number: G09G3/346 ,  G09G3/2007 ,  G09G3/2022 ,  G09G3/2059 ,  G09G2330/10 ,  H04N5/7441

Abstract: A DMD display system includes an inverse gamma look-up-table (50) for converting raster scanned, gamma corrected video data of 8 bits to 12 bits inverse gamma data with 8 most significant bits (msb) and 4 least significant bits (lsb). The 8 msb are coupled to the micromirror of the DMD display (10) and the four lsb are delayed and halved such that one half of the lsb is added to the next pixel in the horizontal scan and one-half of the lsb is added to the next vertical pixel one line length delayed due to degamma. For each input intensity in, the output intensity in will be displayed on the DMD device. If the degamma was perfect and there was no lack of bits, the value displayed in the DMD would be some other value N1. We compute the difference between N and N1 and distribute this difference (error) among the neighboring pixels. The error can be distributed among the neighbors in various ways. One implementation is shown in Fig. 4. A further advantage of the present invention is that the defect compensation can be performed as part of this algorithm. For this, the DMD coordinates of defective pixels need to be known and the error diffusion needs to be modified to account for the fact that at those locations the pixel displays either bright (stuck ON), dark (stuck OFF) or neutral (flat pixel).

公开(公告)号：EP0651581A3

公开(公告)日：1996-05-08

申请号：EP94116987.2

申请日：1994-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gove, Robert J ,  Doherty, Donald B. ,  Heimbuch, Scott D. ,  Urbanus, Paul M. ,  Marshall, Stephen W. ,  Markandey, Vishal ,  Meyer, Richard C.

IPC: H04N7/26

CPC classification number: H04N9/3147 ,  H04N5/14 ,  H04N5/4401 ,  H04N5/7458 ,  H04N7/0122 ,  H04N19/30 ,  H04N19/423 ,  H04N19/436 ,  H04N19/61 ,  H04N21/4402 ,  H04N2005/7466

Abstract: A digital television system (10) is provided. System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into component form by composite video interface and separation circuit (16). The component video signals are converted to digital component video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital component video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital component video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c). Each formatter (24a) through (24c) may comprise a plurality of first in-first out buffer memories (34a) through (34j). One of each channel signal processors (22a) through (22d) may be coupled to two of first in-first out buffer memories (34a) through (34j). Additionally, each formatter (24a) through (24c) may comprise channel data format units (38a) through (38d), each associated with a channel of, for example, display (24a). Channel data format units (38a) through (38d) are coupled to appropriate of first in-first out buffer memories (34a) through (34j) via multiplexers (36a) through (36d). Each formatter (24a) through (24c) may remove overlap between channels of system (10) and may format the processed video signal into appropriate channels for displays (26a) through (26c).

公开(公告)号：EP0651580A3

公开(公告)日：1996-05-08

申请号：EP94116986.4

申请日：1994-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gove, Robert J. ,  Doherty, Donald B. ,  Marshall, Stephen W. ,  Davis, Carl W. ,  Egan, Joseph G. ,  Meyer, Richard C. ,  Sampsell, Jeffrey B. ,  Heimbuch, Scott D. ,  Markandey, Vishal

IPC: H04N7/26

CPC classification number: H04N9/3147 ,  H04N5/14 ,  H04N5/4401 ,  H04N5/7458 ,  H04N7/0122 ,  H04N19/30 ,  H04N19/423 ,  H04N19/436 ,  H04N19/61 ,  H04N21/4402 ,  H04N2005/7466

Abstract: A system (30) for packing data into a video processor is provided. System (30) comprises demultiplexer (32), first and second first in-first out buffer memories (34) and (36), and multiplexer (38). Demultiplexer (32) divides a field of video data into first and second parts (42) and (44). First and second parts (42) and (44) are stored in first first in-first out buffer memories (34) and (36), respectively. Multiplexer (38) combines one line from first first in-first out buffer memory (34) with one line from second first in-first out buffer memory (36) to form a single line for processing.

公开(公告)号：EP0710019A2

公开(公告)日：1996-05-01

申请号：EP95117189.1

申请日：1995-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gove, Robert J. ,  Markandey, Vishal

IPC: H04N5/74

CPC classification number: G09G3/346 ,  G06K15/1252 ,  G06K2215/111 ,  G09G3/002 ,  G09G3/20 ,  G09G3/2022 ,  G09G2340/0407 ,  G09G2340/0414 ,  G09G2340/0421 ,  G09G2340/0442 ,  G09G2360/02 ,  H04N1/1903 ,  H04N1/193 ,  H04N1/1934 ,  H04N5/4401 ,  H04N5/7458 ,  H04N7/01 ,  H04N2005/7466

Abstract: A digital micromirror device (60) for displaying a wide television image comprising a 16:9 array of mirror elements suspended over a substrate, each mirror element having at least one address electrode formed on the substrate between the substrate and the mirror element. An array of memory cells (62) is formed on the substrate, each memory cell in communication with at least one address electrode. An array of input shift registers (64) in communication with the memory cells (62) is formed on the substrate for receiving a series of input image data words and for driving the image data to the memory cells (62). The digital micromirror device (60) enables the efficient reproduction of standard and wide-television images.

公开(公告)号：EP0661889A2

公开(公告)日：1995-07-05

申请号：EP95100053.8

申请日：1995-01-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gove, Robert J. ,  Markandey, Vishal ,  Meyer, Richard C.

IPC: H04N9/64

CPC classification number: H04N9/646

Abstract: A system (10) for processing pixel video data having a selectable number of bits is provided. The system (10) comprises first, second and third video processors (12), (14) and (16). The first video processor (12) receives and processes pixel data of a luminance video signal. The second video processor (14) may receive and process pixel data of a chrominance video signal and may generate one of first, second and third video signal outputs. The third video processor (16) may process the chrominance video signal and may also generate at least two of the output video signals.

Abstract translation: 提供一种用于处理具有可选位数的像素视频数据的系统（10）。 系统（10）包括第一，第二和第三视频处理器（12），（14）和（16）。 第一视频处理器（12）接收并处理亮度视频信号的像素数据。 第二视频处理器（14）可以接收和处理色度视频信号的像素数据，并且可以生成第一，第二和第三视频信号输出中的一个。 第三视频处理器（16）可以处理色度视频信号，并且还可以产生至少两个输出视频信号。