公开(公告)号：US20200013744A1

公开(公告)日：2020-01-09

申请号：US16181374

申请日：2018-11-06

Applicant: Unimicron Technology Corp.

Inventor： Yu-Chung Hsieh ,  Chun-Hsien Chien ,  Yu-Hua Chen

IPC: H01L23/00 ,  H01L21/027 ,  H01L21/768

Abstract: A circuit board element including an insulating layer, a circuit layer, a protective layer, a plurality of solder balls, and a dielectric layer is provided. The circuit layer is disposed on the insulating layer. The protective layer is disposed on the circuit layer and has a plurality of openings exposing the circuit layer. The plurality of solder balls are disposed on the protective layer and embedded in the corresponding openings. The dielectric layer is disposed between the solder balls and the protective layer. A manufacturing method of a circuit board element is also provided.

公开(公告)号：US10141224B2

公开(公告)日：2018-11-27

申请号：US15821666

申请日：2017-11-22

Applicant: Unimicron Technology Corp.

Inventor： Dyi-Chung Hu ,  Yin-Po Hung ,  Ra-Min Tain ,  Yu-Hua Chen

IPC: H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48

Abstract: An interconnection structure and a manufacturing method thereof are provided. The method includes the following steps. First, a substrate having a first surface and a second surface opposite to each other is provided. Then, a conductive through via extended from the first surface to the second surface is formed in the substrate. Then, a portion of the substrate is removed from the first surface to expose a portion of the conductive through via. Then, a dielectric layer is formed on the substrate, and the dielectric layer covers the exposed conductive through via. Then, an opening is formed in the dielectric layer, wherein the opening exposes a portion of the conductive through via, and the top surface of the conductive through via protrudes from the bottom surface of the opening. Then, a conductive layer is formed in the opening.

公开(公告)号：US20180096889A1

公开(公告)日：2018-04-05

申请号：US15821666

申请日：2017-11-22

Applicant: Unimicron Technology Corp.

Inventor： Dyi-Chung Hu ,  Yin-Po Hung ,  Ra-Min Tain ,  Yu-Hua Chen

IPC: H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L21/76879 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827

Abstract: An interconnection structure and a manufacturing method thereof are provided. The method includes the following steps. First, a substrate having a first surface and a second surface opposite to each other is provided. Then, a conductive through via extended from the first surface to the second surface is formed in the substrate. Then, a portion of the substrate is removed from the first surface to expose a portion of the conductive through via. Then, a dielectric layer is formed on the substrate, and the dielectric layer covers the exposed conductive through via. Then, an opening is formed in the dielectric layer, wherein the opening exposes a portion of the conductive through via, and the top surface of the conductive through via protrudes from the bottom surface of the opening. Then, a conductive layer is formed in the opening.

公开(公告)号：US20180070452A1

公开(公告)日：2018-03-08

申请号：US15256757

申请日：2016-09-06

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Shih-Lian Cheng ,  Yu-Hua Chen ,  Cheng-Ta Ko ,  Jui-Jung Chien ,  Wei-Tse Ho

IPC: H05K3/06 ,  H05K3/10 ,  H05K3/42 ,  H05K3/24 ,  G03F7/16 ,  G03F7/20 ,  G03F7/09 ,  G03F7/32 ,  G03F7/40 ,  G03F1/50 ,  G03F1/76

CPC classification number: G03F1/50 ,  G01K7/24 ,  G01K15/007 ,  G03F7/2032 ,  G03F7/2047 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/107 ,  H05K3/1275 ,  H05K3/182 ,  H05K3/241 ,  H05K3/422

Abstract: A manufacturing method of a circuit substrate is provided. A substrate is provided. A positive photoresist layer is coated on the substrate. Once exposure process is performed on the positive photoresist layer disposed on the substrate so as to simultaneously form concaves with at least two different depths.

公开(公告)号：US09887153B2

公开(公告)日：2018-02-06

申请号：US15257897

申请日：2016-09-06

Applicant: Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Cheng-Ta Ko

IPC: H05K1/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/096 ,  H05K2201/10378

Abstract: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.

公开(公告)号：US09859159B2

公开(公告)日：2018-01-02

申请号：US14644197

申请日：2015-03-10

Applicant: Unimicron Technology Corp.

Inventor： Dyi-Chung Hu ,  Yin-Po Hung ,  Ra-Min Tain ,  Yu-Hua Chen

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L21/76879 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827

Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a substrate, a conductive through via, a dielectric layer, and a conductive layer. The substrate has a first surface and a second surface opposite to each other. The conductive through via is disposed in the substrate and extended from the first surface beyond the second surface. The dielectric layer is disposed on the substrate, wherein the dielectric layer has an opening exposing a portion of the conductive through via. The top surface of the conductive through via protrudes from the bottom surface of the opening. The conductive layer is disposed in the opening and connected to the conductive through via.

公开(公告)号：US09578742B1

公开(公告)日：2017-02-21

申请号：US14821819

申请日：2015-08-10

Applicant: Unimicron Technology Corp.

Inventor： Shih-Liang Cheng ,  Dyi-Chung Hu ,  Yu-Hua Chen

IPC: H05K1/11 ,  H05K3/00 ,  H05K1/02 ,  H05K3/40 ,  H05K1/09 ,  H05K1/18

CPC classification number: H05K1/11 ,  H05K1/0298 ,  H05K1/182 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/007 ,  H05K3/0097 ,  H05K3/045 ,  H05K3/107 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0195 ,  H05K2203/025 ,  H05K2203/107 ,  H05K2203/1476

Abstract: A method for manufacturing a circuit board structure is provided. First, a first circuit layer is formed on a carrier. Then, a first dielectric layer is formed on the carrier and the first circuit layer. Thereafter, at least one first hole is formed in the first dielectric layer to expose a portion of the first circuit layer. Then, a second dielectric layer is formed on the first dielectric layer and the first circuit layer. Thereafter, at least one trench and at least one second hole are formed in the second dielectric layer, in which the trench exposes a portion of the first dielectric layer, and the second hole exposes the portion of the first circuit layer. The second hole is disposed in the first hole. Then, a metal layer is formed to fill the trench and the second hole.

Abstract translation: 提供一种制造电路板结构的方法。 首先，在载体上形成第一电路层。 然后，在载体和第一电路层上形成第一电介质层。 此后，在第一电介质层中形成至少一个第一孔以暴露第一电路层的一部分。 然后，在第一电介质层和第一电路层上形成第二电介质层。 此后，在第二电介质层中形成至少一个沟槽和至少一个第二孔，其中沟槽露出第一电介质层的一部分，并且第二孔露出第一电路层的部分。 第二孔设置在第一孔中。 然后，形成金属层以填充沟槽和第二孔。

公开(公告)号：US20160190050A1

公开(公告)日：2016-06-30

申请号：US14583755

申请日：2014-12-28

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min Tain ,  Dyi-Chung Hu ,  Yu-Hua Chen

IPC: H01L23/498 ,  H01L21/3105 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing an interposer includes the following steps. Conductive beads is filled in a blind via of a substrate and a solder layer of each conductive bead is melted so as to form a solder post in the blind via. A metal ball of each conductive bead is inlaid in the corresponding solder post such that the solder post and the metal balls inlaid therein construct a conductive though via. Two surfaces of the substrate are planarized such that two ends of the conductive through via are exposed to the two surfaces of the substrate respectively and are flush with the two surfaces of the substrate respectively. A redistribution layer is manufactured at each surface of the substrate such that the two ends of each conductive through via connect the redistribution layers respectively. Besides, an interposer and a chip package structure applied the interposer are also provided.

Abstract translation: 一种用于制造插入件的方法包括以下步骤。 导电珠填充在基板的盲孔中，并且每个导电珠的焊料层熔化，以在盲孔中形成焊料柱。 每个导电珠的金属球镶嵌在相应的焊料柱中，使得焊接柱和镶嵌在其中的金属球构成导电的通孔。 基板的两个表面被平坦化，使得导电通孔的两个端部分别暴露于基板的两个表面，并分别与基板的两个表面齐平。 在衬底的每个表面处制造再分布层，使得每个导电通孔的两端分别连接重新分布层。 此外，还提供了应用了插入器的插入器和芯片封装结构。