公开(公告)号：JPH11145747A

公开(公告)日：1999-05-28

申请号：JP30218497

申请日：1997-11-04

Applicant: YAMAHA CORP

Inventor： KISHII TATSUYA ,  NORO MASAO

IPC: H03G3/12

Abstract: PROBLEM TO BE SOLVED: To provide a gain control circuit which causes no error to an expected value of gain and can secure its stable operation, even for a low level of power voltage. SOLUTION: A current operational amplifier 12 outputs currents IOUT1 and IOUT2 , which are proportional to an input signal VIN. An adder circuit 20 adds together both currents IOUT1 and IOUT2 and outputs a signal VOUT that is accordant with the addition result. The amplifier 12 contains plural FETs which output the currents IOUT1 and IOUT2 , a current mirror which supplies a gate voltage to the FETs to acquire the currents IOUT1 and IOUT2 , and a switching control means, which supplies a gate voltage in place of the gate voltage to the FET that outputs the current IOUT1 to turn off the FET, in response to a switching signal CON.

公开(公告)号：JPH0567976A

公开(公告)日：1993-03-19

申请号：JP28079191

申请日：1991-10-01

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M3/04

Abstract: PURPOSE:To improve the S/N and to reduce the oversampling ratio in the D/A converter which utilizes the oversampling technology and the noise shaping technology. CONSTITUTION:A level detection circuit 22 detects that a digital input value is less than a prescribed level and a shift control circuit 26 and a shift circuit 20 increase the digital value by a prescribed value in response to the detection output of the level detection circuit 22. Moreover, an analog output extracted from a low pass filter 18 is attenuated corresponding to a prescribed quantity at an attenuation control circuit 32 and an attenuator 30 in response to the detection output of the level detection circuit 22. The attenuation control is implemented as to a digital signal at an output side of a noise shaper 12.

公开(公告)号：JPH04179317A

公开(公告)日：1992-06-26

申请号：JP30790290

申请日：1990-11-14

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M3/04

Abstract: PURPOSE:To improve an S/N by connecting a substrate electrode member to either a ground power lead wire or a non-ground power lead wire and connecting a decoupling capacitor between the substrate electrode member and the other power lead wire. CONSTITUTION:When the substrate electrode member 20 is connected to the non-ground power lead wire T1, the decoupling capacitor 30 is connected between the substrate electrode member 20 and the ground power lead wire T2. The decoupling capacitor 30 operates to set high frequency noise entering the non-ground power lead wire T1 and the substrate electrode member 20 free to a ground potential-side. Thus, the potential of the non-ground power lead wire T1 and that of the substrate electrode member 20 hardly fluctuate by high frequency noise and the introduction of noise to a waveform shaping output and a system clock signal is considerably reduced.

公开(公告)号：JPH04177915A

公开(公告)日：1992-06-25

申请号：JP30557390

申请日：1990-11-09

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M3/04 ,  H01L23/50 ,  H03M3/02

Abstract: PURPOSE:To improve the S/N by specifying the relation of position of an input/ output lead of a package and a clock lead so as to reduce invasion of noise from the input lead to the output lead and the clock lead. CONSTITUTION:An input lead 24 is arranged in the vicinity of a 1st corner A1 located at one end of one side of a package 22, an output lead 28 is arranged in the vicinity of a 2nd corner A2 in a diagonal position to the 1st corner A1 and a clock lead 26 is arranged in the vicinity of a 3rd corner A3 located at the other end of the one side. Thus, the parting distance of the clock lead 26 and the output lead 28 is taken large with respect to the input lead 24 and invasion of noise to a waveform shaping output or a system clock signal depending on a digital input is remarkably reduced. Thus, the S/N is considerably improved.

公开(公告)号：JPH04115722A

公开(公告)日：1992-04-16

申请号：JP23519190

申请日：1990-09-05

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M3/04 ,  H03M3/02

Abstract: PURPOSE:To reduce noise at non-signal by detecting the presence of a signal as an input of a noise shaper and stopping a dither function when no signal exists so as to clear the data in the noise shaper. CONSTITUTION:When a detection circuit 30 detects the absence of a digital signal based on an output A of a filter 10, a detection output NS goes to 1 and a control switch 32 is in off-control and a data in a noise shaper 16 is cleared. When the switch 32 is in the off-state, the addition of an AC waveform signal D is stopped by an adder 12, an output A1 of the adder 12 reaches a non-signal state and all the data in the noise shaper 16 are cleared. Thus, even when the noise shaper 16 makes feedback operation, the content of the register always keep the same zero state, the noise included in the output is minimized. When the circuit 30 detects the presence of the digital signal based on the output A of the filter 10, a detection output NS goes to 0, the switch 32 is turned on and the noise shaper 16 is acted normally.