公开(公告)号：US20020164876A1

公开(公告)日：2002-11-07

申请号：US10054697

申请日：2002-01-18

Inventor： Hans S. Walitzki ,  Howard W. Hogle ,  Wing S. Luk ,  Claudian R. Nicolesco

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/31053 ,  B24B37/044 ,  B81C1/00611 ,  B81C2201/0119 ,  C09G1/02 ,  H01L21/2007

Abstract: According to the invention, a method for preparing multicrystalline substrates as nullhandle wafersnull for subsequent bonding to nulldevice layernull quality materials is disclosed. In one step, starting with a suitable substrate such as multicrystalline silicon, the substrate surface is prepared for layer transfers by using a novel CMP method in which, after a suitable period of polishing at elevated pH, a surfactant and rinse material is gradually introduced into the slurry to lower pH and remove wear materials from the slurry. In another step, a filler layer of polycrystalline silicon is transferred to the face of the polished substrate to a predetermined thickness, thus filling in surface defects remaining after the initial CMP step, and a subsequent CMP polishing step is performed. By these steps, multicrystalline substrates can be prepared with surface roughness of twenty Angstroms or less, which is suitable for defect-free bonding to device-layer materials in this embodiment.

Abstract translation: 根据本发明，公开了一种用于制备多晶基板作为用于后续结合到“器件层”质量材料的“处理晶片”的方法。 在一个步骤中，从诸如多晶硅的合适的衬底开始，通过使用新的CMP方法制备用于层转移的衬底表面，其中在升高的pH下在适当的抛光周期后，将表面活性剂和漂洗材料逐渐引入 该浆料降低pH并从浆料中除去磨损材料。 在另一步骤中，将多晶硅的填料层转移到抛光的衬底的表面至预定厚度，从而填充在初始CMP步骤之后残留的表面缺陷，并进行随后的CMP研磨步骤。 通过这些步骤，可以制备具有20埃或更小的表面粗糙度的多晶衬底，其适合于在该实施例中与器件层材料的无缺陷结合。

公开(公告)号：KR1020040066107A

公开(公告)日：2004-07-23

申请号：KR1020047006248

申请日：2002-10-29

Applicant: 브레우어 사이언스 인코포레이션

Inventor： 시흐우셍 ,  램제임스이써드

IPC: H01L21/31 ,  H01L21/4763

CPC classification number: B81C1/0046 ,  B81C1/00611 ,  B81C2201/0119 ,  C08G59/68 ,  C08L63/00 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/31051 ,  H01L21/312

Abstract: 본 발명은 접촉 평탄화 공정에서 사용되는 때 경화 공정 동안 휘발성 부산물을 거의 발생하지 않는 평탄화 재료에 관한 것이다. 상기 재료는 평탄화공정 동안에 광조사에 의하여 또는 열에 의하여 경화될 수 있고, 단량체, 올리고머 또는 이들의 혼합물을 포함하고, 임의적인 성분으로서 가교제 및 유기 반응성 용매를 포함한다. 상기 용매가 사용되는 경우, 이는 상기 단량체 또는 올리고머와 화학적으로 반응함으로써 경화 공정 동안 상기 중합체 기질의 일부가 된다. 상기 평탄화 재료는 다마신, 듀얼 다마신, 이층 및 다층 소자, 마이크로 전자 기계 시스템(MEMS), 패키징, 광학 소자, 광자 소자, 광전자 소자, 마이크로 전자 소자, 및 센서 소자의 제작을 위하여 사용될 수 있다.

公开(公告)号：EP3012621A1

公开(公告)日：2016-04-27

申请号：EP14003605.4

申请日：2014-10-22

Applicant: Bundesrepublik Deutschland, vertreten durch das Bundesministerium für Wirtschaft und Technologie, dieses vertreten durch den Präsidenten der

Inventor： Bütefisch, Sebastian ,  Weimann, Thomas ,  Danzebrink, Hans-Ulrich ,  Busch, Ingo

IPC: G01N23/227 ,  B81C1/00 ,  H01L21/02

CPC classification number: G01N23/2273 ,  B81C1/00611 ,  B81C2201/0119 ,  B81C2201/0195

Abstract: Die Erfindung betrifft ein Verfahren zum Herstellen eines Bauteiles (16) mit einer Oberfläche (14), die eine vorbestimmte Oberflächenrauigkeit aufweist, wobei das Verfahren die folgenden Schritte aufweist:
a) Bereitstellen eines ersten Substrates (2) mit einer ersten Oberfläche (4), die die vorbestimmte Oberflächenrauigkeit aufweist,
b) Aufbringen wenigstens einer Materialschicht (8, 10) auf die erste Oberfläche (4) des ersten Substrates (2),
c) Entfernen des ersten Substrates (2).

Abstract translation: 本发明涉及一种用于制造具有表面具有预定表面粗糙度的组分（16）（14），所述方法包括以下步骤：a）提供具有第一表面（4）的第一衬底（2）， 具有预定的表面粗糙度，b）所述第一衬底（2）的第一表面（4）上施加材料（8中的至少一个层，10），c）除去所述第一衬底（2）。

公开(公告)号：EP1440465B1

公开(公告)日：2015-07-08

申请号：EP02802484.2

申请日：2002-10-29

Applicant: Brewer Science, Inc.

Inventor： Shih, Wu-Sheng ,  Lamb, James, E., III ,  Daffron, Mark

IPC: H01L21/3105 ,  H01L21/312 ,  C08L63/00

CPC classification number: B81C1/0046 ,  B81C1/00611 ,  B81C2201/0119 ,  C08G59/68 ,  C08L63/00 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/31051 ,  H01L21/312

Abstract: The present invention is directed towards planarization materials that produce little or no volatile byproducts during the hardening process when used in contact planarization processes. The materials can be hardened by photo-irradiation or by heat during the planarization process, and they include one or more types of monomers, oligomers, or mixtures thereof, an optional cross-linker, and an optional organic reactive solvents. The solvent, if used, is chemically reacted with the monomers or oligomers and thus becomes part of the polymer matrix during the curing process. These materials can be used for damascene, dual damascene, bi-layer, and multi-layer applications, microelectromechanical system (MEMS), packaging, optical devices, photonics, optoelectronics, microelectronics, and sensor devices fabrication.

公开(公告)号：EP1440465A4

公开(公告)日：2010-08-25

申请号：EP02802484

申请日：2002-10-29

Applicant: BREWER SCIENCE INC

Inventor： SHIH WU-SHENG ,  LAMB JAMES E III ,  DAFFRON MARK

IPC: H05K3/22 ,  B81C1/00 ,  C08G59/68 ,  C08L63/00 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/4763

CPC classification number: B81C1/0046 ,  B81C1/00611 ,  B81C2201/0119 ,  C08G59/68 ,  C08L63/00 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/31051 ,  H01L21/312

Abstract: The present invention is directed towards planarization materials that produce little or no volatile byproducts during the hardening process when used in contact planarization processes. The materials can be hardened by photo-irradiation or by heat during the planarization process, and they include one or more types of monomers, oligomers, or mixtures thereof, an optional cross-linker, and an optional organic reactive solvents. The solvent, if used, is chemically reacted with the monomers or oligomers and thus becomes part of the polymer matrix during the curing process. These materials can be used for damascene, dual damascene, bi-layer, and multi-layer applications, microelectromechanical system (MEMS), packaging, optical devices, photonics, optoelectronics, microelectronics, and sensor devices fabrication.

公开(公告)号：EP1460036A1

公开(公告)日：2004-09-22

申请号：EP02805883.2

申请日：2002-12-16

Applicant: Sony Corporation

Inventor： IKEDA, Koichi, c/o Sony Corporation ,  KINOSHITA, Takashi, c/o Sony Corporation

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81C1/00611 ,  B81B2201/042 ,  B81B2203/0118 ,  B81C2201/0109 ,  B81C2201/0119 ,  B81C2201/0125

Abstract: The present invention provides manufacturing methods of electrostatic type MEME devices, in which planarizing the surface of a driving side electrode, reducing fluctuations in the shape of a beam, improving the performance and the uniformity are aimed at.
A manufacturing method according to the present invention includes the steps of: forming a substrate side electrode on a substrate, forming a fluid film before or after forming a sacrificial layer, further forming a beam having a driving side electrode on a planarized surface of the fluid film, and finally, removing the sacrificial layer.

Abstract translation: 本发明提供静电型MEME器件的制造方法，其中平面化驱动侧电极的表面，减小光束形状的波动，提高性能和均匀性。 根据本发明的制造方法包括以下步骤：在基板上形成基板侧电极，在形成牺牲层之前或之后形成流体膜，进一步在平坦化形成具有驱动侧电极的光束 流体膜的表面，最后去除牺牲层。

公开(公告)号：EP1440465A1

公开(公告)日：2004-07-28

申请号：EP02802484.2

申请日：2002-10-29

Applicant: Brewer Science, Inc.

Inventor： WU-SHENG, Shih ,  Lamb, James, E., III ,  Daffron, Mark

IPC: H01L21/4763

CPC classification number: B81C1/0046 ,  B81C1/00611 ,  B81C2201/0119 ,  C08G59/68 ,  C08L63/00 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/31051 ,  H01L21/312

Abstract: The present invention is directed towards planarization materials that produce little or no volatile byproducts during the hardening process when used in contact planarization processes. The materials can be hardened by photo-irradiation or by heat during the planarization process, and they include one or more types of monomers, oligomers, or mixtures thereof, an optional cross-linker, and an optional organic reactive solvents. The solvent, if used, is chemically reacted with the monomers or oligomers and thus becomes part of the polymer matrix during the curing process. These materials can be used for damascene, dual damascene, bi-layer, and multi-layer applications, microelectromechanical system (MEMS), packaging, optical devices, photonics, optoelectronics, microelectronics, and sensor devices fabrication.

公开(公告)号：EP2536168A3

公开(公告)日：2013-01-16

申请号：EP12169041.6

申请日：2012-05-23

Applicant: ROBERT BOSCH GMBH

Inventor： Diamond, Brett M. ,  Laermer, Franz ,  Doller, Andrew J. ,  Daley, Michael J. ,  Stetson, Michael ,  Muza, John M.

IPC: H04R19/00 ,  H04R19/04 ,  H04R31/00

CPC classification number: H04R19/005 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81C1/00158 ,  B81C2201/0119 ,  B81C2201/0177 ,  B81C2203/0714 ,  B81C2203/075 ,  B81C2203/0778 ,  H04R19/04 ,  H04R31/00

Abstract: A method of manufacturing a microphone using epitaxially grown silicon. A monolithic wafer structure is provided. A wafer surface of the structure includes poly-crystalline silicon in a first horizontal region and mono-crystalline silicon in a second horizontal region surrounding a perimeter of the first horizontal region. A hybrid silicon layer is epitaxially deposited on the wafer surface. Portions of the hybrid silicon layer that contact the poly-crystalline silicon use the poly-crystalline silicon as a seed material and portions that contact the mono-crystalline silicon use the mono-crystalline silicon as a seed material. As such, the hybrid silicon layer includes both mono-crystalline silicon and poly-crystalline silicon in the same layer of the same wafer structure. A CMOS/membrane layer is then deposited on top of the hybrid silicon layer.

公开(公告)号：EP2453038A1

公开(公告)日：2012-05-16

申请号：EP10191391.1

申请日：2010-11-16

Applicant: The Swatch Group Research and Development Ltd.

Inventor： Bourban, Stewes ,  Richard, David ,  Gilomen, Beat ,  Steinmüller, Detlef ,  Drexel, Herwig ,  Steinmüller, Doris ,  Ghodbane, Slimane

IPC: C23C16/27 ,  D04B15/14 ,  B81B3/00

CPC classification number: H01L21/02527 ,  B81B3/0075 ,  B81B2201/035 ,  B81C2201/0119 ,  C23C16/27 ,  C23C16/278 ,  C23C16/279 ,  G04B15/14

Abstract: Method for coating micromechanical components of a micromechanical system, in particular a watch movement, comprising:
• providing a substrate (4) component to be coated;
• providing said component with a first diamond coating (2) doped with boron ;
• providing said component with a second diamond coating (3); wherein :
• said second diamond coating (3) is provided by CVD in a reaction chamber;
during CVD deposition, during the last portion of the growth process, a controlled increase of the carbon content within the reaction chamber is provided, thereby providing an increase of the sp2/sp3 carbon (6) bonds up to an sp2 content substantially between 1% and 45%. Corresponding micromechanical components are also provided.

Abstract translation: 用于涂覆微机械部件的微型机械系统的，尤其是手表机芯的方法，包括：€¢提供底物（4）待涂布部件; €¢提供所述组分与第一金刚石涂层（2）掺杂有硼; €¢提供所述组分与第二金刚石涂层（3）; worin：€¢所述第二金刚石涂层（3）由CVD在反应室中提供的; CVD沉积期间，生长过程的负载部分期间，所述反应室中的碳含量的受控增加设置，从而在SP2 / sp 3碳（6）键直至sp2含量基本上之间1％的增加提供 和45％。 因此，提供对应的微机械部件。

公开(公告)号：EP1846321B1

公开(公告)日：2010-12-22

申请号：EP05702532.2

申请日：2005-01-31

Applicant: Freescale Semiconductor Inc.

Inventor： RENAUD, Philippe ,  BERTRAND, Isabelle

IPC: B81C1/00 ,  H01L21/20 ,  H01L21/762 ,  H01L21/268 ,  C30B25/10

CPC classification number: B81C1/00611 ,  B81C2201/0119 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02667

Abstract: In the field of sensor fabrication, it is known to form a silicon-on-insulator starting structure from which fabrication of the sensor based. The present invention provides a method of forming a silicon-on-insulator structure comprising a substrate (102) having an insulating layer (104) patterned thereon. A silicon oxide layer (106) is then deposited over the patterned insulating layer (104) before silicon is grown over both an exposed surface of the substrate (102) as well as the silicon oxide layer (106), mono-crystalline silicon (108) forming on the exposed parts of the substrate (102) and polysilicon (110) forming on the silicon oxide layer (106). After depositing a capping layer 112 over the structure, the wafer is heated, whereby the polysilicon (110) re-crystallises to form mono-crystalline silicon (108), resulting in the insulating layer 104 being buried beneath mono-crystalline silicon.