公开(公告)号：EP3238232A1

公开(公告)日：2017-11-01

申请号：EP15820157.4

申请日：2015-12-22

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： LANDIS, Stéphan ,  POSSEME, Nicolas ,  NOURI, Lamia

IPC: H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L31/0236 ,  H01L33/00 ,  G03F7/00 ,  B81C1/00

CPC classification number: H01L21/266 ,  B81C1/00103 ,  B81C1/0046 ,  B81C1/00587 ,  B81C2201/0136 ,  B81C2201/0153 ,  B82Y10/00 ,  B82Y40/00 ,  C23C14/042 ,  C23C14/48 ,  G03F7/0002 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L31/02363 ,  H01L31/0392 ,  H01L31/1852 ,  H01L33/007 ,  H01L33/20 ,  H01L33/22 ,  Y02E10/50

Abstract: The invention relates, in particular, to a method for producing subsequent patterns in an underlying layer (120), the method comprising at least a step of producing previous patterns in a printable layer (110) overlying the underlying layer (120), the production of the previous patterns comprising the nanoimprinting of the printable layer (110) and leaving in place a continuous layer formed by the printable layer (110) and covering the underlying layer (120), characterised in that it comprises the following step: at least one step of modifying the underlying layer (120) by ion implantation (421) in the underlying layer (120), the implantation (421) being carried out through the printable layer (110) comprising the subsequent patterns, the implantation (421) parameters being chosen so as to form, in the underlying layer (120), implanted areas (122) and non-implanted areas, the non-implanted areas defining the subsequent patterns and having a geometry that is dependent on the previous patterns.

Abstract translation: 本发明尤其涉及一种用于在底层（120）中产生随后的图案的方法，所述方法至少包括在覆盖下层（120）的可印刷层（110）中产生先前图案的步骤，所述产品 所述先前图案包括可印刷层（110）的纳米压印并留下由可印刷层（110）形成并覆盖下层（120）的连续层，其特征在于其包括以下步骤：至少一个 通过在所述下层（120）中的离子注入（421）来修改所述下层（120）的步骤，所述注入（421）通过包括所述后续图案的可印刷层（110）来执行，所述注入 以便在下层（120）中形成注入区域（122）和非注入区域，非注入区域限定后续图案并且具有依赖于前面的图案的几何形状 tterns。

公开(公告)号：EP2300356A2

公开(公告)日：2011-03-30

申请号：EP09761543.9

申请日：2009-04-21

Applicant: Robert Bosch GmbH

Inventor： KRAMER, Torsten ,  AHLES, Marcus ,  GRUNDMANN, Armin ,  KNESE, Kathrin ,  BENZEL, Hubert ,  SCHUERMANN, Gregor ,  ARMBRUSTER, Simon

IPC: B81C1/00

CPC classification number: B81C1/00158 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81C2201/0115 ,  B81C2201/0136 ,  G01L9/0042

Abstract: The invention proposes a particularly simple, cost-effective method for producing a micromechanical membrane structure with access from the rear of the substrate. Said method is based on a p-doped Si substrate (1) and comprises the following process steps: n-doping of at least one continuous lattice-type region (2) of the substrate surface; porous etching of a substrate region (5) below the n-doped lattice structure (2); creation of a cavity (7) in said substrate region (5) below the n-doped lattice structure (2); growing of a first monocrystalline silicon epitaxial layer (8) on the n-doped lattice structure (2). The invention is characterised in that at least one opening (6) in the n-doped lattice structure (2) is dimensioned in such a way that it is not closed by the growing first epitaxial layer (8) and instead forms an access opening (9) to the cavity (7); an oxide layer (10) is created on the cavity wall; A rear face access (13) to the cavity (7) is created, the oxide layer (10) acting as an etch stop layer; and the oxide layer (10) is removed in the region of the cavity (7) producing a rear face access (13) to the membrane structure (14) lying above the cavity (7).

公开(公告)号：EP1967488A3

公开(公告)日：2008-09-17

申请号：EP08104525.4

申请日：2004-11-02

Applicant: ROBERT BOSCH GMBH

Inventor： Lammel, Gerhard ,  Benzel, Hubert ,  Schaefer, Frank ,  Armbruster, Simon ,  Schelling, Christoph ,  Brasas, Joerg

IPC: B81B3/00

CPC classification number: B81B3/007 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00658 ,  B81C2201/0115 ,  B81C2201/0116 ,  B81C2201/0136

Abstract: Die Erfindung beschreibt ein Verfahren zur Herstellung eines Halbleiterbauelements, insbesondere eines mikromechanischen Membransensors, sowie ein Halbleiterbauelement nach einem der beanspruchten Herstellungsverfahren, mit einem Halbleiterträger, einer Membran und einer Kaverne.

公开(公告)号：EP1306348B1

公开(公告)日：2007-05-16

申请号：EP01125193.1

申请日：2001-10-24

Applicant: ROBERT BOSCH GMBH

Inventor： Artmann, Hans ,  Pannek, Thorsten

IPC: B81B3/00

CPC classification number: B81C1/0069 ,  B81B2201/0278 ,  B81B2203/0127 ,  B81C2201/0115 ,  B81C2201/0136

公开(公告)号：EP1544163A3

公开(公告)日：2006-07-05

申请号：EP04105448.7

申请日：2004-11-02

Applicant: ROBERT BOSCH GMBH

Inventor： BENZEL, Hubert ,  SCHAEFER, Frank ,  ARMBRUSTER, Simon ,  Lammel, Gerhard ,  SCHELLING, Christoph ,  BRASAS, Joerg

IPC: B81B3/00

CPC classification number: B81C1/00158 ,  B81B3/007 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0116 ,  B81C2201/0136

Abstract: Die Anmeldung beschreibt ein Herstellungsverfahren eines insbesondere mikromechanischen Halbleiterbauelements sowie ein mit diesem Verfahren hergestelltes Halbleiterbauelement. Zur Herstellung des Halbleiterbauelements ist vorgesehen, dass auf einem Halbleiterträger ein strukturiertes Stabilisierungselement mit wenigstens einer Öffnung erzeugt wird. Die Öffnung ist dabei so angebracht, dass sie den Zugang zu einem mit einer ersten Dotierung aufweisenden ersten Bereich im Halbleiterträger erlaubt. Weiterhin ist ein selektives Herauslösen wenigstens eines Teils des mit der ersten Dotierung versehenen Halbleitermaterials aus dem ersten Bereich des Halbleiterträger vorgesehen. Darüber hinaus wird mittels einer ersten Epitaxieschicht, die auf das Stabilisierungselement aufgebracht wird, eine Membran oberhalb des ersten Bereichs erzeugt. Wenigstens ein Teil des ersten Bereichs dient in einem weiteren Verfahrensschritt dazu, eine Kaverne unterhalb des Stabilisierungselement zu erzeugen. Der Kern der Anmeldung besteht nun darin, das strukturierte Stabilisierungselement mittels einer zweiten Epitaxieschicht, die auf dem Halbleiterträger aufgebracht wird, zu erzeugen.

公开(公告)号：EP0678905A3

公开(公告)日：1997-10-08

申请号：EP95102347.2

申请日：1995-02-20

Applicant: ROCKWELL INTERNATIONAL CORPORATION

Inventor： Hays, Kenneth M.

IPC: H01L21/308

CPC classification number: G01L9/0019 ,  B81C1/00801 ,  B81C2201/0136 ,  B81C2201/014 ,  H03H3/007 ,  Y10S148/012

Abstract: A dissolved wafer micromachining process is modified by providing an etch control seal around the perimeter of a heavily doped micromechanical structure formed on a substrate. The micromechanical structure is fabricated on a wafer using conventional methods including the formation of a trench that surrounds and defines the shape of the micromechanical structure in the substrate. The etch control seal comprises a portion of the substrate in the form of a raised ring extending around the perimeter of the micromechanical structure and its defining trench. Selected raised areas of the heavily doped micromechanical structure and the top of the raised etch control seal are bonded to a second substrate. A selective etch is then used to dissolve the first substrate so that the heavily doped micromechanical structure remains attached to the second substrate only at the bonded areas. The etch control seal reduces exposure of the micromechanical structure and bonded areas to the etch by preventing the etch from contacting the heavily doped structure until the etch leaks through the dissolving floor of the trench. This occurs only during the final stages of the substrate dissolution step, thus minimizing exposure of the micromechanical structure and bonded areas to the damaging effects of the etch. Use of an etch control seal increases design flexibility and improves micromechanical device yield and quality in a dissolved wafer fabrication process.

Abstract translation: 用于微加工工艺的蚀刻控制密封件包括可溶于选择性蚀刻（10）的基底，在其上形成具有凸起区域（12）的微机械结构。 在结构周围的衬底上的凸起环（16）具有比衬底更大的蚀刻电阻，并且结合到环和凸起区域的第二衬底（18）也具有更大的耐蚀刻性。 结合环形成蚀刻控制密封件（20），以通过选择性蚀刻在第一衬底去除期间保护结构。 还要求保护的是如上所述的微加工工艺的粘合组件，其中没有规定在第一基板上形成具有凸起区域的结构的性质。

公开(公告)号：US11756793B2

公开(公告)日：2023-09-12

申请号：US16906206

申请日：2020-06-19

Applicant: Hitachi High-Tech Corporation

Inventor： Yohei Ishii ,  Kathryn Maier ,  Medhat Khalil

IPC: H01L21/306 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/30621 ,  H01L21/3065 ,  H01L21/30604 ,  H01L21/32136 ,  H01L21/32138 ,  B81C2201/0136 ,  H01L21/308

Abstract: A semiconductor device manufacturing method includes the steps of etching a semiconductor material by using plasma, forming a damage layer on the semiconductor material, and removing the damage layer such that a relatively low temperature process can form a fine pattern with a vertical cross section using a compound semiconductor material or the like.

公开(公告)号：US20120018779A1

公开(公告)日：2012-01-26

申请号：US12740607

申请日：2008-10-13

Applicant: Franz Laermer ,  Tino Fuchs ,  Christina Leinenbach

Inventor： Franz Laermer ,  Tino Fuchs ,  Christina Leinenbach

IPC: H01L29/06 ,  H01L21/20

CPC classification number: B81C1/00103 ,  B81B2203/0384 ,  B81C2201/0136

Abstract: A method for producing micromechanical patterns having a relief-like sidewall outline shape or an angle of inclination that is able to be set, the micromechanical patterns being etched out of a SiGe mixed semiconductor layer that is present on or deposited on a silicon semiconductor substrate, by dry chemical etching of the SiGe mixed semiconductor layer; the sidewall outline shape of the micromechanical pattern being developed by varying the germanium proportion in the SiGe mixed semiconductor layer that is to be etched; a greater germanium proportion being present in regions that are to be etched more strongly; the variation in the germanium proportion in the SiGe mixed semiconductor layer being set by a method selected from the group including depositing a SiGe mixed semiconductor layer having varying germanium content, introducing germanium into a silicon semiconductor layer or a SiGe mixed semiconductor layer, introducing silicon into a germanium layer or an SiGe mixed semiconductor layer and/or by thermal oxidation of a SiGe mixed semiconductor layer.

Abstract translation: 一种用于生产具有凸起状侧壁轮廓形状或能够被设定的倾斜角的微机械图案的方法，从存在于或沉积在硅半导体衬底上的SiGe混合半导体层中蚀刻微机械图案， 通过干法化学蚀刻SiGe混合半导体层; 通过改变要蚀刻的SiGe混合半导体层中的锗比例来显影微机械图案的侧壁轮廓形状; 存在于要被更强蚀刻的区域中更大的锗比例; SiGe混合半导体层中的锗比例的变化通过选自包括沉积具有不同锗含量的SiGe混合半导体层，将锗引入到硅半导体层或SiGe混合半导体层中的方法来设置，将硅引入 锗层或SiGe混合半导体层和/或通过SiGe混合半导体层的热氧化。

公开(公告)号：US07843025B2

公开(公告)日：2010-11-30

申请号：US12359904

申请日：2009-01-26

Applicant: Hubert Benzel ,  Frank Schaefer ,  Simon Armbruster ,  Gerhard Lammel ,  Christoph Schelling ,  Joerg Brasas

Inventor： Hubert Benzel ,  Frank Schaefer ,  Simon Armbruster ,  Gerhard Lammel ,  Christoph Schelling ,  Joerg Brasas

IPC: H01L21/00

CPC classification number: B81B3/007 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00658 ,  B81C2201/0115 ,  B81C2201/0116 ,  B81C2201/0136

Abstract: A manufacturing method for a micromechanical semiconductor element includes providing on a semiconductor substrate a patterned stabilizing element having at least one opening. The opening is arranged such that it allows access to a first region in the semiconductor substrate, the first region having a first doping. Furthermore, a selective removal of at least a portion of the semiconductor material having the first doping out of the first region of the semiconductor substrate is provided. In addition, a membrane is produced above the first region using a first epitaxy layer applied on the stabilizing element. In a further method step, at least a portion of the first region is used to produce a cavity underneath the stabilizing element. In this manner, the present invention provides for the production of the patterned stabilizing element by means of a second epitaxy layer, which is applied on the semiconductor substrate.

Abstract translation: 微机电半导体元件的制造方法包括在半导体衬底上提供具有至少一个开口的图案化稳定元件。 开口被布置成使得其允许接近半导体衬底中的第一区域，第一区域具有第一掺杂。 此外，提供了选择性地去除半导体衬底的第一区域中具有第一掺杂的半导体材料的至少一部分。 此外，使用施加在稳定元件上的第一外延层，在第一区域上方产生膜。 在另一方法步骤中，第一区域的至少一部分用于在稳定元件下方产生空腔。 以这种方式，本发明提供了通过施加在半导体衬底上的第二外延层来生产图案化的稳定元件。

公开(公告)号：US20090127640A1

公开(公告)日：2009-05-21

申请号：US12359904

申请日：2009-01-26

Applicant: Hubert Benzel ,  Frank Schaefer ,  Simon Armbruster ,  Gerhard Lammel ,  Christoph Schelling ,  Joerg Brasas

Inventor： Hubert Benzel ,  Frank Schaefer ,  Simon Armbruster ,  Gerhard Lammel ,  Christoph Schelling ,  Joerg Brasas

IPC: H01L29/84 ,  H01L21/3213

CPC classification number: B81B3/007 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00658 ,  B81C2201/0115 ,  B81C2201/0116 ,  B81C2201/0136

Abstract: A manufacturing method for a micromechanical semiconductor element includes providing on a semiconductor substrate a patterned stabilizing element having at least one opening. The opening is arranged such that it allows access to a first region in the semiconductor substrate, the first region having a first doping. Furthermore, a selective removal of at least a portion of the semiconductor material having the first doping out of the first region of the semiconductor substrate is provided. In addition, a membrane is produced above the first region using a first epitaxy layer applied on the stabilizing element. In a further method step, at least a portion of the first region is used to produce a cavity underneath the stabilizing element. In this manner, the present invention provides for the production of the patterned stabilizing element by means of a second epitaxy layer, which is applied on the semiconductor substrate.

Abstract translation: 微机电半导体元件的制造方法包括在半导体衬底上提供具有至少一个开口的图案化稳定元件。 开口被布置成使得其允许接近半导体衬底中的第一区域，第一区域具有第一掺杂。 此外，提供了选择性地去除半导体衬底的第一区域中具有第一掺杂的半导体材料的至少一部分。 此外，使用施加在稳定元件上的第一外延层，在第一区域上方产生膜。 在另一方法步骤中，第一区域的至少一部分用于在稳定元件下方产生空腔。 以这种方式，本发明提供了通过施加在半导体衬底上的第二外延层来生产图案化的稳定元件。