公开(公告)号：WO2013029041A3

公开(公告)日：2013-06-20

申请号：PCT/US2012052503

申请日：2012-08-27

Applicant: AMPHENOL CORP ,  PANIAGUA JOSE RICARDO

Inventor： PANIAGUA JOSE RICARDO

IPC: G06F17/50

CPC classification number: H05K1/116 ,  G06F17/5081 ,  G06F2217/82 ,  H05K1/0225 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/0005 ,  H05K3/0047 ,  H05K3/10 ,  H05K3/42 ,  H05K2201/0784 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/09718 ,  H05K2201/09727 ,  H05K2203/0207 ,  H05K2203/0242 ,  Y10T29/49165

Abstract: A printed circuit board for carrying high frequency signals. Conducting structures of the printed circuit board are shaped within breakout regions to limit impedance discontinuities in the signal paths between vias and conductive traces within the printed circuit board. Values of parameters of traces or anti-pads, for example, may be adjusted to provide a desired impedance. The specific values selected as part of designing a printed circuit board may match the impedance of the breakout region to that of the via. The parameters for which values are selected may include the trace width, thickness, spacing, length over an anti-pad or angle of exit from the breakout region.

Abstract translation: 用于传输高频信号的印刷电路板。 印刷电路板的导电结构在突出区域内成形以限制印刷电路板内的通孔和导电迹线之间的信号路径中的阻抗不连续性。 例如，可以调整迹线或防焊垫的参数值以提供期望的阻抗。 选择作为设计印刷电路板的一部分的特定值可以将突破区域的阻抗与通孔的阻抗相匹配。 其值被选择的参数可以包括迹线宽度，厚度，间隔，反焊盘上的长度或从中断区域退出的角度。

公开(公告)号：WO2012153839A1

公开(公告)日：2012-11-15

申请号：PCT/JP2012/062139

申请日：2012-05-11

Applicant: 株式会社フジクラ ,  山本 敏

Inventor： 山本　敏

IPC: H05K1/11 ,  H01L23/12

CPC classification number: H05K1/116 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/1461 ,  H05K1/0272 ,  H05K1/115 ,  H05K3/002 ,  H05K3/101 ,  H05K2201/0784 ,  H05K2201/09836 ,  H05K2201/09845 ,  H05K2201/10378 ,  H05K2203/107 ,  H05K2203/128 ,  H01L2924/00

Abstract: 　本発明の貫通配線基板は、第一主面及び第二主面を有する単一の基板と、前記基板の厚み方向とは異なる方向に延設された第一部位と、貫通配線の一方の端部を構成する第二部位と、貫通配線の他方の端部を構成する第三部位と、を少なくとも有し、前記第一主面及び前記第二主面を結ぶように前記基板の内部に設けられた複数の貫通配線とを備え、前記第二部位は、前記第一主面に対して略垂直であり前記第一主面にて露出し、前記第三部位は、前記第二主面に対して略垂直であり前記第二主面にて露出し、前記複数の貫通配線の長さは、略同じである。

Abstract translation: 通过该布线板设置有具有第一主表面和第二主表面的单个基板，以及设置在基板内部以连接第一主表面和第二主表面的多个馈通线， 具有至少第一部分沿除了基板的厚度方向以外的方向延伸，第二部分构成馈通线的一端，第三部分构成馈通线的另一端。 第二部分大致垂直于第一主表面并且在第一主表面处露出，第三部分大致垂直于第二主表面并且在第二主表面处露出。 多个馈通线具有大致相同的长度。

公开(公告)号：WO2011092620A1

公开(公告)日：2011-08-04

申请号：PCT/IB2011/050295

申请日：2011-01-24

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ZHOU, Guofu ,  HOEVENAARS, Albericus, Antonius, Maria ,  VAN ABEELEN, Frank, Anton ,  VAN PIETERSON, Liesbeth ,  HORNIX, Eefje, Janet

Inventor： ZHOU, Guofu ,  HOEVENAARS, Albericus, Antonius, Maria ,  VAN ABEELEN, Frank, Anton ,  VAN PIETERSON, Liesbeth ,  HORNIX, Eefje, Janet

IPC: H05K1/03 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K1/18 ,  A41D27/085 ,  H05K1/0287 ,  H05K1/038 ,  H05K2201/0281 ,  H05K2201/029 ,  H05K2201/0784 ,  H05K2201/09236 ,  H05K2201/10106

Abstract: The invention relates to an electronic network comprising a row of two or more electronic components (121, 122, 123) each having an input terminal (131, 141) and an output terminal (132, 142). All input terminals are interconnected with a conductive input line (151), and all output terminals are interconnected with a conductive output line (152), the input and output lines having a uniform and substantially the same electrical resistance per unit length. The input line is arranged to allow electric charge to flow to each electronic component via the input terminal (131) of the first electronic component (121), and the output line is arranged to allow electric charge to flow away from each electronic component via the output terminal (142) of the last electronic component (123). The electronic network enables a uniform performance of the electronic components, particularly when the input and output lines have a relatively high electrical resistance. The electronic network is therefore particularly suitable for use in an electronic textile (100), wherein the input and output lines are electrically conductive yarns that are interwoven in a textile carrier (110) on which the electronic components are mounted.

Abstract translation: 本发明涉及一种电子网络，包括一排两个或多个电子部件（121,122,123），每个电子部件具有输入端子（131,141）和输出端子（132,142）。 所有输入端子与导电输入线路151互连，所有输出端子与导电输出线路（152）互连，输入和输出线路每单位长度具有均匀且基本相同的电阻。 输入线被布置成允许电荷经由第一电子部件（121）的输入端子（131）流动到每个电子部件，并且输出线被布置成允许电荷经由所述电子部件从每个电子部件流出 输出终端（142）。 电子网络能够实现电子部件的均匀性能，特别是当输入和输出线路具有相对较高的电阻时。 因此，电子网络特别适用于电子纺织品（100），其中输入和输出线是交织在其上安装有电子部件的纺织品载体（110）中的导电纱线。

公开(公告)号：WO2018214024A1

公开(公告)日：2018-11-29

申请号：PCT/CN2017/085498

申请日：2017-05-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： LI, Yunze ,  YANG, Ni ,  DENG, Ming ,  LI, Zhiyong ,  LIU, Mengqiu ,  LI, Hui

IPC: G09G3/36 ,  G02F1/13

CPC classification number: G09G3/20 ,  G02F1/1345 ,  G02F2001/13629 ,  G09F13/00 ,  G09G2300/0426 ,  G09G2320/0223 ,  H05K1/11 ,  H05K2201/0784 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/10128

Abstract: The present application discloses a display panel having a plurality of wirings (1,2) in the fan-out area (300) respectively connected to a plurality of signal lines (100) in the display area (200), each of the plurality of wirings in the fan-out area (300) configured to transmit a signal to one of a plurality of subpixels through one of the plurality of signal lines (100) in the display area (200); and a plurality of bonding pads (400) respectively connected to the plurality of wirings (1,2), configured to boned the plurality of wirings (1,2) with a driver integrated circuit. The plurality of wirings (1,2) are grouped into a plurality of groups of wirings (1,2) comprising a first group of a plurality of first wirings (1) and a second group of a plurality of second wirings (2). The plurality of first wirings (1) are made of a first conductive material. The plurality of second wirings (2) are made of a second conductive material. The second conductive material has a resistivity greater than that of the first conductive material.

公开(公告)号：WO2016034212A1

公开(公告)日：2016-03-10

申请号：PCT/EP2014/068639

申请日：2014-09-02

Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (publ)

Inventor： LIGANDER, Per ,  LARSSON, Ingolf ,  BERGSTEN, Tomas ,  NYSTRÖM, Olle ,  WESTIN, Torbjörn

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0242 ,  H01P5/085 ,  H05K1/0243 ,  H05K1/0251 ,  H05K1/115 ,  H05K1/184 ,  H05K3/4038 ,  H05K3/42 ,  H05K2201/0784 ,  H05K2201/10583

Abstract: The present invention relates to a microwave signal transition component (1) having a first signal conductor side (2) and a second signal conductor side (3). The signal transition component (1) is arranged for transfer of microwave signals from the first signal conductor side (2) to the second signal conductor side (3). The transfer component (1) comprises at least one, at least partly circumferentially running, electrically conducting frame (4), a dielectric filling (5) positioned at least partly within said conducting frame (4), at least one filling aperture (6; 6a, 6b) running through the dielectric filling, and, for each filling aperture (6; 6a, 6b), an electrically conducting connection (7; 7a, 7b) that at least partly is positioned within said filling aperture (6; 6a, 6b). The present invention also relates to a method for manufacturing a microwave signal transition component according to the above.

Abstract translation: 本发明涉及具有第一信号导体侧（2）和第二信号导体侧（3）的微波信号过渡分量（1）。 信号转换组件（1）用于将微波信号从第一信号导体侧（2）传送到第二信号导体侧（3）。 转移组件（1）包括至少一个至少部分周向运行的导电框架（4），至少部分地位于所述导电框架（4）内的电介质填充物（5），至少一个填充孔（6; 穿过电介质填充物的每个填充孔（6; 6a，6b）中的导电连接（7; 7a，7b）至少部分地位于所述填充孔（6; 6a，6b） 图6b）。 本发明还涉及根据上述的微波信号转换部件的制造方法。

公开(公告)号：WO1990006853A1

公开(公告)日：1990-06-28

申请号：PCT/EP1989001526

申请日：1989-12-12

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  KAPPEL, Andreas

Inventor： SIEMENS AKTIENGESELLSCHAFT

IPC: B41J02/05

CPC classification number: H05K1/0265 ,  B41J2/14072 ,  B41J2/1601 ,  B41J2/1623 ,  B41J2202/11 ,  H05K2201/0784 ,  H05K2201/09727

Abstract: The choice of appropriate dimensions for a transition structure (ÜV) in a conductor-path layout on a thin-film substrate, the transition structure connecting the closely spaced conductor paths (LA) in the region of the heating elements (RH) with the widely spaced conductor paths (LB) in the region of the bonded contacts, enables the conductor-path input resistance (Li) to be made as uniform as possible, at the same time keeping it low. This is achieved by establishing a dimension-determination specification which, for a given set of input data, i.e. the conductor-path widths (da, db) and gap widths (Sa, Sb) in the two zones, and the gap width (Sv) in the transition structure (ÜV), gives the conductor width (dv) in the transition structure as the output.

Abstract translation: 在薄膜基板上的导体路径布局中对于过渡结构（ÜV）的适当尺寸的选择，将加热元件（RH）区域中紧密间隔的导体路径（LA）与广泛地连接的过渡结构 在接合触点的区域中的间隔导体路径（LB）使导体路径输入电阻（Li）尽可能均匀，同时保持低电平。 这通过建立尺寸确定规范来实现，对于给定的一组输入数据，即两个区域中的导体路径宽度（da，db）和间隙宽度（Sa，Sb）以及间隙宽度（Sv ）在过渡结构（ÜV）中，将过渡结构中的导体宽度（dv）作为输出。

公开(公告)号：KR1020090073771A

公开(公告)日：2009-07-03

申请号：KR1020070141816

申请日：2007-12-31

Applicant: 엘지디스플레이 주식회사

Inventor： 김현철 ,  홍진철

IPC: G02F1/1345

CPC classification number: G02F1/1345 ,  H01L27/124 ,  H01L2924/0002 ,  H05K1/117 ,  H05K2201/0784 ,  H05K2201/09727 ,  H01L2924/00

Abstract: An array substrate for a liquid crystal display device is provided to increase resistance in a central portion of gate or data link areas and decrease resistance in an outer line, thereby removing a problem of not charging. One link line corresponding to between the first link line and the n/2 link line(DDL1~DDLn/2) is defined as the k link line(DLLk). A link line opposite to the k link line and corresponding to between the n/2 link line and the n link line is defined as the I link line. The first to k link lines and the I to n link lines have one or two refractive portions. The k to l link lines do not have refractive portions.

Abstract translation: 提供了一种用于液晶显示装置的阵列基板，以增加栅极或数据链路区域的中心部分的电阻，并降低外线的电阻，从而消除不充电的问题。 对应于第一链接线和n / 2链路线（DDL1〜DDLn / 2）之间的一条链路线被定义为k链路线（DLLk）。 与k链路线相对的并且对应于n / 2链路线和n链路线之间的链路线被定义为I链路线。 第一个到k个链接线和一个到第n个链接线具有一个或两个折射部分。 k至l连接线不具有折射部分。

公开(公告)号：US20170273172A1

公开(公告)日：2017-09-21

申请号：US15500160

申请日：2014-09-02

Applicant: Telefonaktiebolaget LM Ericsson (publ)

Inventor： Per Ligander ,  Tomas Bergsten ,  Ingolf Larsson ,  Olle Nyström ,  Torbjörn Westin

IPC: H05K1/02 ,  H05K3/42 ,  H05K1/11

CPC classification number: H01P11/003 ,  H01P1/045 ,  H01P1/047 ,  H01P5/085 ,  H01P11/005 ,  H05K1/0242 ,  H05K1/0243 ,  H05K1/0251 ,  H05K1/115 ,  H05K1/184 ,  H05K3/4038 ,  H05K3/42 ,  H05K2201/0784 ,  H05K2201/10583

Abstract: The present invention relates to a microwave signal transition component (1) having a first signal conductor side (2) and a second signal conductor side (3). The signal transition component (1) is arranged for transfer of microwave signals from the first signal conductor side (2) to the second signal conductor side (3). The transfer component (1) comprises at least one, at least partly circumferentially running, electrically conducting frame (4), a dielectric filling (5) positioned at least partly within said conducting frame (4), at least one filling aperture (6; 6a, 6b) miming through the dielectric filling, and, for each filling aperture (6; 6a, 6b), an electrically conducting connection (7; 7a, 7b) that at least partly is positioned within said filling aperture (6; 6a, 6b). The present invention also relates to a method for manufacturing a microwave signal transition component according to the above.

公开(公告)号：US09491852B2

公开(公告)日：2016-11-08

申请号：US13007493

申请日：2011-01-14

Applicant: Benjamin B. Lyon ,  Shih Chang Chang ,  Martin Paul Grunthaner

Inventor： Benjamin B. Lyon ,  Shih Chang Chang ,  Martin Paul Grunthaner

IPC: G06F3/041 ,  H05K1/02

CPC classification number: H05K1/0242 ,  G06F3/0412 ,  G06F3/0416 ,  G06F2203/04108 ,  G09G3/2092 ,  H05K1/0265 ,  H05K2201/0784 ,  H05K2201/09272 ,  H05K2201/09727 ,  Y10T29/49155

Abstract: The border routing of conductive traces in devices, such as displays, touch sensor panels, and touch screens, to improve border area space usage, thereby reducing device size, and to reduce trace resistance, thereby improving device operation, is disclosed. The conductive traces can form a staggered stair-step configuration in the device border area, in which the average widths of the traces can be different from each other and each trace can have segments with different widths. The conductive traces can be coupled to an active area of the device to transmit signals to and from the active area in accordance with a device operation. The varying widths can help improve the border area space usage, reduce trace resistance, and reduce the differences in resistance between traces.

Abstract translation: 公开了诸如显示器，触摸传感器面板和触摸屏等设备中导电迹线的边界布线，以改善边界区域空间的使用，从而减少设备尺寸，并降低走线电阻，从而改善器件的操作。 导电迹线可以在器件边界区域中形成交错的阶梯结构，其中迹线的平均宽度可以彼此不同，并且每个迹线可以具有不同宽度的段。 导电迹线可以耦合到设备的有效区域，以根据设备操作向有源区域发送信号和从有源区域发送信号。 变化的宽度可以帮助改善边界区域空间的使用，减少走线电阻，并减少迹线之间的电阻差异。

公开(公告)号：US20160111214A1

公开(公告)日：2016-04-21

申请号：US14645357

申请日：2015-03-11

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sang Soo PARK ,  Min Cheol PARK

IPC: H01G4/30 ,  H05K1/11 ,  H05K1/18 ,  H01G4/12 ,  H05K1/02

CPC classification number: H01G4/30 ,  H01G2/065 ,  H01G4/012 ,  H01G4/1227 ,  H05K1/0216 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/0784

Abstract: A multilayer ceramic capacitor may include a ceramic body having first to third dielectric layers, first and third internal electrodes disposed to be partially exposed to an upper surface of the ceramic body, second and fourth internal electrodes disposed to be partially exposed to a lower surface of the ceramic body, internal resistance electrodes disposed on the third dielectric layers and partially exposed to the upper surface of the ceramic body, first and third external electrodes disposed on the ceramic body to be connected to the first and third internal electrodes, second and fourth external electrodes disposed to be connected to the second and fourth internal electrodes. The first and third external electrodes are electrically connected to each other by the internal resistance electrodes.

Abstract translation: 多层陶瓷电容器可以包括具有第一至第三介电层的陶瓷体，设置成部分地暴露于陶瓷体的上表面的第一和第三内部电极，被设置为部分地暴露于陶瓷体的下表面的第二和第四内部电极 所述陶瓷体，设置在所述第三电介质层上并且部分地暴露于所述陶瓷体的上表面的内部电阻电极，设置在陶瓷体上以连接到所述第一和第三内部电极的第一和第三外部电极，第二和第四外部电极 设置成连接到第二和第四内部电极的电极。 第一和第三外部电极通过内部电阻电极彼此电连接。