SYSTEMS AND METHODS FOR ON-STATIONARY SURFACE DETECTION

    公开(公告)号:US20250035668A1

    公开(公告)日:2025-01-30

    申请号:US18595004

    申请日:2024-03-04

    Abstract: A method for determining whether an electronic device is located on a stationary surface includes generating, by a first motion sensor of an electronic device, first sensor data over an acquisition time window. The method includes determining, by a first feature detection circuit of the electronic device, at least one first orientation-independent feature for the acquisition time window based on the first sensor data. The method further includes executing, by a first classifying circuit of the electronic device, a first machine learning classification to determine whether the electronic device is steady or is in motion. And the method further includes, in response to determining the electronic device is steady, executing, by a second classifying circuit of the electronic device, a second machine learning classification to determine whether the electronic device is on a stationary surface or is on a semi-stationary surface based on the at least one first orientation-independent feature.

    SYSTEMS AND METHODS FOR ON-STATIONARY SURFACE DETECTION

    公开(公告)号:US20250035665A1

    公开(公告)日:2025-01-30

    申请号:US18357851

    申请日:2023-07-24

    Abstract: A method includes generating, by a first motion sensor of an electronic device, first sensor data over an acquisition time window; generating first process data by processing the first sensor data to determine whether or not the electronic device is located on a stationary surface; determining whether or not the electronic device is in a stable state based on the first process data. The stable state is indicative of whether the electronic device has remained on a stationary surface or not for a first predefined time. The method includes stopping the processing of the first sensor data in response to determining that the electronic device has been in the stable state for a second predefined time.

    Process, voltage, and temperature invariant time-to-digital converter with sub-gate delay resolution

    公开(公告)号:US12212324B2

    公开(公告)日:2025-01-28

    申请号:US18330871

    申请日:2023-06-07

    Abstract: A control circuit and a method for delaying an electronic signal are provided, along with a time-to-digital converter including the control circuit. The example control circuit includes a first delay circuit having a first plurality of delay elements electrically connected in series and configured to generate a first control voltage associated with a first delay time. The control circuit further includes a second delay circuit having a second plurality of delay elements electrically connected at least in part in series. The second delay circuit is configured to generate a second control voltage associated with a second delay time. A first group of delay elements within the second plurality of delay elements exhibits the first delay time based on the first control voltage, and a second group of the second plurality of delay elements exhibits a second delay time based at least in part on the second control voltage.

    Low overhead mesochronous digital interface

    公开(公告)号:US12210373B2

    公开(公告)日:2025-01-28

    申请号:US18165855

    申请日:2023-02-07

    Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.

    MEMORY PROGRAM SECURIZATION METHOD
    57.
    发明申请

    公开(公告)号:US20250028653A1

    公开(公告)日:2025-01-23

    申请号:US18776561

    申请日:2024-07-18

    Inventor: Jawad BENHAMMADI

    Abstract: A method of securization of programs in a memory embedded within a microcontroller includes writing a boot program into a first area of the memory and writing at least one additional program into at least one second area of the memory. One or more values of a first register are modified to provide a write protection of the first and second areas. A prohibition against modification of the one or more values of the first register is then implemented when those values are associated with a write protection state of the first area.

    Protection of an integrated circuit

    公开(公告)号:US12205650B2

    公开(公告)日:2025-01-21

    申请号:US18173472

    申请日:2023-02-23

    Abstract: An integrated circuit comprises a memory device including a memory plane having non-volatile memory cells and being non-observable in read mode from outside the memory device, a controller, internal to the memory device, configured to detect the memorized content of the memory plane, and when the memorized content contains locking content, automatically lock any access to the memory plane from outside the memory device, the integrated circuit then being in a locked status, and authorize delivery outside the memory device of at least one sensitive datum stored in the memory plane.

    CIRCUIT FOR VOLTAGE OFFSET COMPENSATION

    公开(公告)号:US20250023531A1

    公开(公告)日:2025-01-16

    申请号:US18352034

    申请日:2023-07-13

    Inventor: Vratislav Michal

    Abstract: A circuit includes a current source, a differential pair of transistors coupled to the current source, an active load, and a current injection circuit. The differential pair of transistors has a first offset voltage and an input transconductance. The current injection circuit is configured to supply a first current and a second current to produce a second offset voltage across the differential pair of transistors opposite the first offset voltage. The first current and the second current has a same thermal dependence as the input transconductance of the differential pair of transistors.

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