公开(公告)号：US20090039986A1

公开(公告)日：2009-02-12

申请号：US11835960

申请日：2007-08-08

Applicant: Telesphor Kamgaing ,  Emile Davies-Venn

Inventor： Telesphor Kamgaing ,  Emile Davies-Venn

IPC: H01P1/04

CPC classification number: H01P1/212 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/48095 ,  H01L2224/48225 ,  H01L2224/48237 ,  H01L2224/49113 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A microelectronic package having a radio frequency (RF) amplifier circuit and, incorporating harmonic rejection filters and matching circuits integrally formed in the package is disclosed. A harmonic rejection filter may comprise a metal-insulator-metal (MIM) capacitor serially coupled between bond pads disposed on a RF amplifier circuit die, a first wire bond coupling a first bond pad to a package output, where the first bond pad is coupled to the output of the RF amplifier, and a second wire bond coupling a second bond pad to a package ground. The harmonic rejection filter may be appropriately configured to filter one or more harmonics at different frequencies.

Abstract translation: 公开了一种具有射频（RF）放大器电路并且并入谐波抑制滤波器和整体形成在封装中的匹配电路的微电子封装。 谐波抑制滤波器可以包括串联连接在RF放大器电路管芯上的接合焊盘之间的金属 - 绝缘体 - 金属（MIM）电容器，将第一接合焊盘耦合到封装输出端的第一引线键合，其中第一接合焊盘耦合 到RF放大器的输出，以及将第二接合焊盘耦合到封装地的第二引线接合。 谐波抑制滤波器可以被适当地配置为滤波不同频率的一个或多个谐波。

公开(公告)号：US20070069835A1

公开(公告)日：2007-03-29

申请号：US11240305

申请日：2005-09-29

Applicant: Telesphor Kamgaing

Inventor： Telesphor Kamgaing

IPC: H03H7/01

CPC classification number: H03H5/02 ,  H01F27/40 ,  H01F2017/0046 ,  H03H2001/0085

Abstract: A technique to provide a compact integration of inductor-capacitor resonator a capacitor having a top plate and a bottom plate embedding a dielectric layer. The top and bottom plates are substantially parallel to each other. An inductor having a first end is coupled to the capacitor at the bottom plate. The inductor has N turns surrounding the bottom plate in a spiral geometry. The inductor is co-planar to one of the top and bottom plates and ends at a second end.

Abstract translation: 一种提供电感器 - 电容谐振器紧凑集成的技术，其具有嵌入介电层的顶板和底板的电容器。 顶板和底板基本上彼此平行。 具有第一端的电感器在底板处耦合到电容器。 电感器以螺旋几何形式围绕底板N圈。 电感器与顶板和底板中的一个共面，并在第二端处终止。

公开(公告)号：US20230207494A1

公开(公告)日：2023-06-29

申请号：US17561726

申请日：2021-12-24

Applicant: Jianyong XIE ,  Andrew P. COLLINS ,  Arghya SAIN ,  Sivaseetharaman PANDI ,  Telesphor KAMGAING

Inventor： Jianyong XIE ,  Andrew P. COLLINS ,  Arghya SAIN ,  Sivaseetharaman PANDI ,  Telesphor KAMGAING

IPC: H01L23/64 ,  H01F27/28 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/645 ,  H01F27/2804 ,  H01L23/15 ,  H01L23/49827

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a first layer that comprises glass. In an embodiment, a second layer comprising glass is over the first layer. In an embodiment, the electronic package further comprises an inductor between the first layer and the second layer.

公开(公告)号：US20230207436A1

公开(公告)日：2023-06-29

申请号：US17561531

申请日：2021-12-23

Applicant: Adel A. ELSHERBINI ,  Telesphor KAMGAING

Inventor： Adel A. ELSHERBINI ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01L23/15 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L23/15 ,  H01L25/0655 ,  H01L23/49838

Abstract: Embodiments disclosed herein include die modules, electronic packages, and systems. In an embodiment, a die module comprises a first substrate and a first die over the first substrate. In an embodiment, the die module further comprises a second die over the first substrate adjacent to the first die. In an embodiment, the die module further comprises a via module through the first substrate. In an embodiment, the via module comprises a second substrate, where the second substrate comprises glass, and a via through the second substrate.

公开(公告)号：US10468737B2

公开(公告)日：2019-11-05

申请号：US15859482

申请日：2017-12-30

Applicant: Georgios C. Dogiamis ,  Sasha N. Oster ,  Adel A. Elsherbini ,  Telesphor Kamgaing

Inventor： Georgios C. Dogiamis ,  Sasha N. Oster ,  Adel A. Elsherbini ,  Telesphor Kamgaing

IPC: H01P5/10 ,  H01P5/107 ,  H01P3/02 ,  H01Q13/08 ,  H01Q13/10

Abstract: Embodiments include waveguide launchers and connectors (WLCs), and a method of forming a WLC. The WLC has a waveguide connector with a waveguide launcher, a taper, and a slot-line signal converter; and a balun structure on the slot-line signal converter, where the taper is on the slot-line signal converter and a terminal end of the waveguide connector to form a channel and a tapered slot. The WLC may have the waveguide connector disposed on the package, and a waveguide coupled to waveguide connector. The WLC may include assembly pads and external walls of the waveguide connector electrically coupled to package. The WLC may have the balun structure convert a signal to a slot-line signal, and the waveguide launcher converts the slot-line signal to a closed waveguide mode signal, and emits the closed signal along channel and propagates the closed signal along taper slot to the waveguide coupled to waveguide connector.

公开(公告)号：US20190190106A1

公开(公告)日：2019-06-20

申请号：US16328524

申请日：2016-09-30

Applicant: TELESPHOR KAMGAING ,  SASHA OSTER ,  Georgios Dogiamis ,  Adel Elsherbini ,  Shawna Liff ,  Aleksandar Aleksov ,  JOHANNA SWAN ,  Brandon Rawlings

Inventor： TELESPHOR KAMGAING ,  SASHA OSTER ,  Georgios Dogiamis ,  Adel Elsherbini ,  Shawna Liff ,  Aleksandar Aleksov ,  JOHANNA SWAN ,  Brandon Rawlings

IPC: H01P1/04 ,  H01P1/02 ,  H01P3/12 ,  H01P11/00

CPC classification number: H01P1/042 ,  H01P1/022 ,  H01P3/12 ,  H01P3/121 ,  H01P3/122 ,  H01P11/002

Abstract: Generally, this disclosure provides apparatus and systems for coupling waveguides to a server package with a modular connector system, as well as methods for fabricating such a connector system. Such a system may be formed with connecting waveguides that turn a desired amount, which in turn may allow a server package to send a signal through a waveguide bundle in any given direction without bending waveguides.

公开(公告)号：US10057796B2

公开(公告)日：2018-08-21

申请号：US14552587

申请日：2014-11-25

Applicant: Adel A. Elsherbini ,  Telesphor Kamgaing ,  Pablo Herrero ,  Bernhard Raaf

Inventor： Adel A. Elsherbini ,  Telesphor Kamgaing ,  Pablo Herrero ,  Bernhard Raaf

IPC: H04W24/08 ,  H04B7/04 ,  H01Q1/24

CPC classification number: H04W24/08 ,  H01Q1/245 ,  H04B7/04

Abstract: Described herein are architectures, platforms and methods for implementing an antenna array with a dynamic polarization adjustment in a portable device.

公开(公告)号：US09853359B2

公开(公告)日：2017-12-26

申请号：US14038202

申请日：2013-09-26

Applicant: Adel A. Elsherbini ,  Telesphor Kamgaing

Inventor： Adel A. Elsherbini ,  Telesphor Kamgaing

IPC: H01Q21/00 ,  H01Q9/04 ,  H01Q21/06

CPC classification number: H01Q9/0414 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15321 ,  H01Q21/0006 ,  H01Q21/065 ,  H01Q21/067 ,  Y10T29/49016

Abstract: An antenna integrated in a package substrate, the antenna comprising an upper antenna element, a lower antenna element and a coupling element disposed between the upper antenna element and the lower antenna element, the coupling element comprising an aperture, and configured to provide a coupling between the upper antenna element and the lower antenna element.

公开(公告)号：US09673268B2

公开(公告)日：2017-06-06

申请号：US13976439

申请日：2011-12-29

Applicant: Andreas Duevel ,  Telesphor Kamgaing ,  Valluri R. Rao ,  Uwe Zillmann

Inventor： Andreas Duevel ,  Telesphor Kamgaing ,  Valluri R. Rao ,  Uwe Zillmann

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/52 ,  H01L29/92 ,  H01L49/02 ,  H01F7/06 ,  H01F5/00 ,  H01L23/522 ,  H01F17/00 ,  H01L27/06 ,  H01L27/08

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F2017/002 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/08 ,  H01L2224/4813 ,  H01L2924/0002 ,  H01L2924/00012

Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.

公开(公告)号：US20150084139A1

公开(公告)日：2015-03-26

申请号：US14129541

申请日：2013-09-25

Applicant: Weng Hong Teh ,  Tarek A. Ibrahim ,  Sarah K. Haney ,  Daniel N. Sobieski ,  Parshuram B. Zantye ,  Chad E. Mair ,  Telesphor Kamgaing

Inventor： Weng Hong Teh ,  Tarek A. Ibrahim ,  Sarah K. Haney ,  Daniel N. Sobieski ,  Parshuram B. Zantye ,  Chad E. Mair ,  Telesphor Kamgaing

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81C1/00246 ,  B81B2201/0271 ,  B81C1/00261 ,  B81C1/00277 ,  H01L21/568 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2924/01079

Abstract: Techniques and mechanisms for providing precisely fabricated structures of a semiconductor package. In an embodiment, a build-up carrier of the semiconductor package includes a layer of porous dielectric material. Seed copper and plated copper is disposed on the layer of porous dielectric material. Subsequent etching is performed to remove copper adjacent to the layer of porous dielectric material, forming a gap separating a suspended portion of a MEMS structure from the layer of porous dielectric material. In another embodiment, the semiconductor package includes a copper structure disposed between portions of an insulating layer or portions of a layer of silicon nitride material. The layer of silicon nitride material couples the insulating layer to another insulating layer. One or both of the insulating layers are each protected from desmear processing with a respective release layer structure.

Abstract translation: 用于提供半导体封装的精确制造结构的技术和机构。 在一个实施例中，半导体封装的积聚载体包括多孔介电材料层。 种子铜和电镀铜设置在多孔电介质材料层上。 进行随后的蚀刻以去除邻近多孔介电材料层的铜，形成将MEMS结构的悬置部分与多孔介电材料层分开的间隙。 在另一个实施例中，半导体封装包括设置在绝缘层的一部分之间或者氮化硅材料层的一部分的铜结构。 氮化硅材料层将绝缘层耦合到另一绝缘层。 每个绝缘层中的一个或两个保护层不受去离子处理的剥离层结构的剥离。