公开(公告)号：KR1020120097829A

公开(公告)日：2012-09-05

申请号：KR1020110017293

申请日：2011-02-25

Applicant: 삼성전자주식회사

Inventor： 김보근 ,  경계현 ,  정재용

IPC: G11C7/22 ,  G11C8/18 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/18

Abstract: PURPOSE: A memory system and a controlling method thereof are provided to efficiently prevent the overlap of a peak current from a plurality of semiconductor memory devices and minimize the operation delay of each semiconductor memory device. CONSTITUTION: Memory devices(MDEV1-MDEVn) include an internal clock generator and a memory. The internal clock generator(IGEN) generates an internal clock by synchronizing with a processor clock in response to the processor clock received from a controller(CNT). A memory is synchronized with the internal clock to generate a peak current. Two or more memory devices generate the internal clock which is activated in a different edge of the processor clock.

Abstract translation: 目的：提供一种存储器系统及其控制方法，以有效地防止来自多个半导体存储器件的峰值电流的重叠，并使每个半导体存储器件的操作延迟最小化。 规定：存储器件（MDEV1-MDEVn）包括内部时钟发生器和存储器。 内部时钟发生器（IGEN）响应于从控制器（CNT）接收的处理器时钟，与处理器时钟同步来产生内部时钟。 存储器与内部时钟同步以产生峰值电流。 两个或多个存储器件产生在处理器时钟的不同边缘被激活的内部时钟。

公开(公告)号：KR1020110066697A

公开(公告)日：2011-06-17

申请号：KR1020090123446

申请日：2009-12-11

Applicant: 삼성전자주식회사

Inventor： 천진영 ,  정재용

IPC: G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: PURPOSE: An address mapping table management method and a memory device thereof are provided to extend the lifetime of the memory device and improve the performance by managing an address mapping table to reduce the elimination frequency of the memory device. CONSTITUTION: The first memory cell array(10) stores data. A wear-leveling controller(40) manages a ware-level. The second memory cell array(60) stores an address mapping table. If a conversion physical address mapped in a physical address of the first memory cell array is changed, a memory control unit(30) stores the movement quantity of an address which has to be moved based on the conversion physical address prior to the change in the address mapping table. The memory control unit maps the physical address to the changed conversion physical address with reference to the address mapping table.

Abstract translation: 目的：提供地址映射表管理方法及其存储器件，以延长存储器件的寿命并通过管理地址映射表来提高性能，以减少存储器件的消除频率。 构成：第一个存储单元阵列（10）存储数据。 磨损均衡控制器（40）管理物品级。 第二存储单元阵列（60）存储地址映射表。 如果映射到第一存储单元阵列的物理地址中的转换物理地址改变，则存储器控制单元（30）根据转换物理地址在存储器单元阵列的改变之前存储必须移动的地址的移动量 地址映射表。 存储器控制单元参考地址映射表将物理地址映射到改变的转换物理地址。

公开(公告)号：KR1020080065116A

公开(公告)日：2008-07-11

申请号：KR1020070002103

申请日：2007-01-08

Applicant: 삼성전자주식회사

Inventor： 공재필 ,  정재용

IPC: G11C16/04 ,  G11C16/10

CPC classification number: G11C11/5628

Abstract: A multi level cell flash memory device and a program method thereof are provided to perform flexible program for various requirements of a system, by performing the program regardless of the sequence of bits of multi bit data. According to a program method of a multi level cell flash memory device, a memory cell selected through plural program procedures is programmed with multi bit data(11,10,01,00). Data to be stored in the selected memory cell in the present program procedure is determined by the data of the selected memory cell and the present program procedure. According to the present program procedure, an address of bits programmed in the present program procedure is detected. The data of the selected memory cell is read. Target data is determined by referring to the detected address and the data of the selected memory cell.

Abstract translation: 提供多级单元闪存器件及其程序方法，通过执行程序来执行用于系统的各种要求的灵活程序，而不管多位数据的位序列如何。 根据多电平单元闪存器件的编程方法，通过多个程序程序选择的存储器单元用多位数据（11,10,01,00）进行编程。 要存储在当前程序过程中的所选存储单元中的数据由所选存储单元的数据和当前的程序程序确定。 根据本程序程序，检测在本程序程序中编程的位地址。 读取所选存储单元的数据。 通过参考检测到的地址和所选存储单元的数据来确定目标数据。

公开(公告)号：KR100813629B1

公开(公告)日：2008-03-14

申请号：KR1020070005259

申请日：2007-01-17

Applicant: 삼성전자주식회사

Inventor： 천진영 ,  정재용 ,  윤치원

IPC: G11C16/16 ,  G11C16/14

CPC classification number: G11C16/22 ,  G11C7/24 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3468

Abstract: An advanced sector protection scheme is provided to improve convenience and stability by restricting write operation for write protection state of sectors through a master cell. A memory cell array is constituted with sectors. A read/write circuit performs read and write operations of the memory cell array. A write protection control block(700) generates a write protection flag signal for a sector to be written. A control logic operates in response to the write protection flag signal, and controls the read/write circuit to perform write operation for the sector to be written selectively. The write protection control block includes a latch circuit(710), a cell array(720) and a check circuit(790). The latch circuit stores write state or write protection state of each sector temporarily. The cell array stores write state or write protection state of each sector permanently. The check circuit outputs the write protection flag signal.

Abstract translation: 提供先进的扇区保护方案，通过限制通过主单元的扇区写保护状态的写操作来提高便利性和稳定性。 存储单元阵列由扇区构成。 读/写电路执行存储单元阵列的读和写操作。 写保护控制块（700）为要写入的扇区产生写保护标志信号。 控制逻辑响应于写保护标志信号进行操作，并且控制读/写电路对要写入的扇区进行选择性的写操作。 写保护控制块包括锁存电路（710），单元阵列（720）和检查电路（790）。 锁存电路临时存储每个扇区的写状态或写保护状态。 单元阵列永久地存储每个扇区的写状态或写保护状态。 检查电路输出写保护标志信号。

公开(公告)号：KR1020080020443A

公开(公告)日：2008-03-05

申请号：KR1020070032854

申请日：2007-04-03

Applicant: 삼성전자주식회사

Inventor： 정기호 ,  정재용 ,  윤치원

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A flash memory device and a multi level cell program method for the same are provided to shorten program time as minimizing the generation of overshoot. According to a multi level cell program method of a flash memory device comprising a plurality of memory cells programmed as one of a plurality of data states, selected memory cells are programmed as a first data state(S1000). Verification for the program is performed(S1100). The selected memory cells are programmed continuously as at least more than two data states having a lower threshold voltage than the first data state(S1200). Verification of the continuous program is performed(S1300).

Abstract translation: 提供了一种闪存器件和用于其的多级单元程序方法，以缩短程序时间，从而最小化过冲的产生。 根据包括被编程为多个数据状态之一的多个存储器单元的闪存器件的多电平单元编程方法，所选存储单元被编程为第一数据状态（S1000）。 执行程序的验证（S1100）。 所选择的存储单元被连续地编程为具有比第一数据状态低的阈值电压的至少两个以上的数据状态（S1200）。 执行连续程序的验证（S1300）。

公开(公告)号：KR1020060028982A

公开(公告)日：2006-04-04

申请号：KR1020040077925

申请日：2004-09-30

Applicant: 삼성전자주식회사

Inventor： 정재용

IPC: G11C16/34

CPC classification number: G11C16/3436 ,  G11C7/1078 ,  G11C16/10 ,  G11C16/14

Abstract: A data detection circuit senses data of a selected memory cell of a memory cell array after programming or erasing operation of the selected memory. A verifier circuit verifies programmed or erased data stored in a data storage unit while the data detector is sensing new programmed or erased data. An independent claim is also included for method of verifying data in non-volatile memory device.

公开(公告)号：KR100506254B1

公开(公告)日：2005-08-10

申请号：KR1020030083060

申请日：2003-11-21

Applicant: 삼성전자주식회사

Inventor： 정재용

IPC: G06F12/00

Abstract: 본 발명은 특권 모드와 비특권 모드의 서로 다른 수행 모드를 제공하는 운영 체제를 구비한 시스템에서 인터럽트를 처리하기 위한 방법에 있어서, 상기 비특권 모드에서 동작하는 임의의 프로세스로에서 소정의 인터럽트를 처리하기 위한 인터럽트 서비스 루틴(ISR)을 등록하는 과정과, 상기 인터럽트 서비스 루틴(ISR)에 대응되는 인터럽트 발생시 이전 프로세스 작업을 일시 중지하고 상기 등록된 인터럽트 서비스 루틴(ISR)을 수행하도록 하는 과정을 포함함을 특징으로 한다.

公开(公告)号：KR100385224B1

公开(公告)日：2003-05-27

申请号：KR1020000075641

申请日：2000-12-12

Applicant: 삼성전자주식회사

Inventor： 정재용 ,  이성수

IPC: G11C16/04

Abstract: PURPOSE: A method for programming a nonvolatile semiconductor memory device is provided to increase a threshold voltage of a parasitic MOS transistor formed between adjacent cells without increasing a word line voltage. CONSTITUTION: According to data bits latched in first and second page buffers(130_0,130_1), a bit line level control signal having a first voltage is generated so that each of first and second bit lines(BL0,BL1) has one of a program voltage and a program prohibition voltage. The first and second bit lines(BL0,BL1) are electrically insulated from the first and second page buffers(130_0,130_1). A bit line level control signal having a second voltage is generated and a current is supplied to the first and second bit lines(BL0,BL1) so that a voltage of a bit line is set higher than the program voltage. A current supply to the first and second bit lines(BL0,BL1) is intercepted and a high voltage is applied to a selecting word line among word lines.

Abstract translation: 目的：提供一种用于对非易失性半导体存储器件进行编程的方法，以增加在相邻单元之间形成的寄生MOS晶体管的阈值电压，而不增加字线电压。 组成：根据锁存在第一和第二页缓冲器（130_0,130_1）中的数据位，产生具有第一电压的位线电平控制信号，使得第一和第二位线（BL0，BL1）中的每一个具有程序 电压和编程禁止电压。 第一和第二位线（BL0，BL1）与第一和第二页缓冲器（130_0,130_1）电绝缘。 产生具有第二电压的位线电平控制信号，并且电流被提供给第一和第二位线（BL0，BL1），使得位线的电压被设定为高于编程电压。 对第一和​​第二位线（BL0，BL1）的电流供应被截断，并且高电压被施加到字线之中的选择字线。

公开(公告)号：KR1020020092487A

公开(公告)日：2002-12-12

申请号：KR1020010031124

申请日：2001-06-04

Applicant: 삼성전자주식회사

Inventor： 김범수 ,  조유근 ,  민상렬 ,  노삼혁 ,  이귀영 ,  김종민 ,  인지현 ,  정재용 ,  이동희 ,  김제성 ,  최종무

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2212/7203

Abstract: PURPOSE: A flash memory management method is provided to consistently restore the data at an emergency state, for example, an abrupt power shut-off, and to prevent a system performance from being lowered in an environment of a frequent data update on a specific page like a DOS file system based on a FAT(File Allocation Table). CONSTITUTION: The method comprises steps of receiving a request of a write operation on a page on which data has been recorded already, performing the write operation on a log block corresponding to a data block including the page, receiving again a request of a write operation on the same page, and performing the write operation on a free space within the log block. The log block is managed by a data structure of a log pointer table. Entries of the log pointer table include a logical address block, log_blk, a corresponding physical address block, phy_blk, of the data block, and logical addresses of corresponding pages within a corresponding log block in an order that the pages of the data block are recorded.

Abstract translation: 目的：提供闪存管理方法，以在紧急状态下持续恢复数据，例如突然的电源关闭，并防止在特定页面上频繁更新数据的环境中降低系统性能 像一个基于FAT（文件分配表）的DOS文件系统。 构成：该方法包括以下步骤：在已经记录了数据的页面上接收写入操作的请求，对与包括页面的数据块相对应的日志块执行写入操作，再次接收写入操作的请求 在同一页面上，并在日志块中的可用空间上执行写入操作。 日志块由日志指针表的数据结构管理。 日志指针表的条目包括数据块的逻辑地址块log_blk，对应的物理地址块phy_blk，以及数据块的页面被记录的顺序的相应日志块内的相应页面的逻辑地址 。

公开(公告)号：KR1020020046320A

公开(公告)日：2002-06-21

申请号：KR1020000075641

申请日：2000-12-12

Applicant: 삼성전자주식회사

Inventor： 정재용 ,  이성수

IPC: G11C16/04

Abstract: PURPOSE: A method for programming a nonvolatile semiconductor memory device is provided to increase a threshold voltage of a parasitic MOS transistor formed between adjacent cells without increasing a word line voltage. CONSTITUTION: According to data bits latched in first and second page buffers(130_0,130_1), a bit line level control signal having a first voltage is generated so that each of first and second bit lines(BL0,BL1) has one of a program voltage and a program prohibition voltage. The first and second bit lines(BL0,BL1) are electrically insulated from the first and second page buffers(130_0,130_1). A bit line level control signal having a second voltage is generated and a current is supplied to the first and second bit lines(BL0,BL1) so that a voltage of a bit line is set higher than the program voltage. A current supply to the first and second bit lines(BL0,BL1) is intercepted and a high voltage is applied to a selecting word line among word lines.

Abstract translation: 目的：提供一种用于编程非易失性半导体存储器件的方法，以增加形成在相邻单元之间的寄生MOS晶体管的阈值电压，而不增加字线电压。 构成：根据锁存在第一和第二页缓冲器（130_0,130_1）中的数据位，产生具有第一电压的位线电平控制信号，使得第一和第二位线（BL0，BL1）中的每一个具有程序 电压和程序禁止电压。 第一和第二位线（BL0，BL1）与第一和第二寻呼缓冲器（130_0,130_1）电绝缘。 产生具有第二电压的位线电平控制信号，并且将电流提供给第一和第二位线（BL0，BL1），使得位线的电压被设置为高于编程电压。 对第一和​​第二位线（BL0，BL1）的电流供应被截取，并且高电压被施加到字线之间的选择字线。