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公开(公告)号：KR1020110138624A
公开(公告)日：2011-12-28
申请号：KR1020100058624
申请日：2010-06-21
Applicant: 삼성전자주식회사
IPC: H01L31/115
CPC classification number: G01T1/24 , H01L24/24 , H01L24/73 , H01L27/14609 , H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L27/14676 , H01L27/14687 , H01L31/085 , H01L2224/16225 , H01L2924/12043 , H01L2924/14 , H01L2924/15788 , H01L2924/00
Abstract: PURPOSE: A large-scaled x-ray detector and a manufacturing method thereof are provided to transfer charges detected in a photo conductor layer corresponding to an on-demand semiconductor joint area to an on-demand semiconductor, thereby accurately realizing an image on a photographing area without a joint. CONSTITUTION: A photo conductor layer(340) generates an electrical signal by an incident x-ray. A common electrode(350) is formed on one side of the photo conductor layer. A plurality of pixel electrodes(342) is formed on the other side of the photo conductor layer. A planar film(330) covers an on-demand semiconductor(320). The planar film is formed on a printed circuit board(310). A plurality of contacts(322) is formed on the lower part of the on-demand semiconductor.
Abstract translation: 目的：提供一种大型X射线检测器及其制造方法，用于将对应于按需半导体接合区域的光导体层中检测出的电荷传送到点播半导体，从而准确地实现拍摄中的图像 没有关节的区域 构成：光导体层（340）通过入射的x射线产生电信号。 公共电极（350）形成在光导体层的一侧。 在光导体层的另一侧上形成有多个像素电极（342）。 平面薄膜（330）覆盖按需半导体（320）。 平面膜形成在印刷电路板（310）上。 在按需半导体的下部形成有多个触点（322）。
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公开(公告)号：KR1020110109066A
公开(公告)日：2011-10-06
申请号：KR1020100028616
申请日：2010-03-30
Applicant: 삼성전자주식회사
IPC: H01L31/115
CPC classification number: H01L31/085 , G01T1/24
Abstract: 산화물 반도체 트랜지스터를 구비한 엑스선 검출기가 개시된다. 개시된 산화물 반도체 트랜지스터를 구비한 엑스선 검출기는, 기판 상에서 직렬로 배치된 산화물 반도체 물질로 형성된 채널을 구비한 산화물 반도체 트랜지스터 및 신호저장 커패시터와 포토컨덕터를 구비한다. 포토컨덕터의 양면에는 각각 픽셀전극 및 공통전극이 형성된다. 상기 채널은 ZnO 또는 ZnO에 Ga, In, Hf, Sn 중 선택된 적어도 하나를 포함하는 화합물로 이루어진 산화물 반도체 채널이다.
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公开(公告)号：KR1020110072270A
公开(公告)日：2011-06-29
申请号：KR1020090129127
申请日：2009-12-22
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L29/786
CPC classification number: H01L29/7869 , H01L29/4908 , H01L29/66969 , H01L29/78696 , H01L29/4232 , H01L29/1025 , H01L29/41725
Abstract: PURPOSE: A transistor, a manufacturing method thereof, and an electronic device including the same are provided to improve the reliability of a flat panel display device by suppressing the property change of a transistor due to light. CONSTITUTION: A channel layer(C1) includes an oxide semiconductor. A source and a drain are contacted with both sides of the channel layer. A gate(G1) corresponds to the channel layer. A gate insulation layer is formed between the channel layer and the gate. A fluorine containing region is located on a contact interface between the channel layer and the gate insulation layer. The fluorine containing region is a region processed with plasma including fluorine.
Abstract translation: 目的：提供晶体管及其制造方法以及包括该晶体管的电子器件，以通过抑制由于光导致的晶体管的特性变化来提高平板显示装置的可靠性。 构成：通道层（C1）包括氧化物半导体。 源极和漏极与沟道层的两侧接触。 栅极（G1）对应于沟道层。 在沟道层和栅极之间形成栅极绝缘层。 含氟区域位于沟道层和栅极绝缘层之间的接触界面上。 含氟区域是用含氟的等离子体处理的区域。
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公开(公告)号：KR1020100124052A
公开(公告)日：2010-11-26
申请号：KR1020090043095
申请日：2009-05-18
Applicant: 삼성전자주식회사
CPC classification number: G06F21/74 , G06F9/30189 , G06F9/322 , G06F2221/2105 , G06F21/00
Abstract: PURPOSE: A security environment device and a method thereof which is independent from platform are provided to switch into security environment by turning on security bit after succeeding branch command. CONSTITUTION: A security monitor(110) watches a call of a security code by a processor(100), and creates a branch instruction. If the branch instruction is successfully operated by the processor, the security monitor makes the security bit on. If the execution of the security code is completed, the security monitor makes the security bit off. A command bypass ROM(120) receives the branch instruction from the security monitor.
Abstract translation: 目的：提供独立于平台的安全环境设备及其方法，以便在后续分支命令之后打开安全位，切换到安全环境。 构成：安全监视器（110）通过处理器（100）监视安全码的呼叫，并创建分支指令。 如果分支指令由处理器成功运行，则安全监视器将使安全位打开。 如果安全代码的执行完成，则安全监视器会使安全位关闭。 命令旁路ROM（120）从安全监视器接收分支指令。
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公开(公告)号：KR1020100007703A
公开(公告)日：2010-01-22
申请号：KR1020090033846
申请日：2009-04-17
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/78696 , H01L29/41725 , H01L29/42312 , H01L29/7869
Abstract: PURPOSE: A channel layer and a transistor including the same are provided to control a threshold voltage and the mobility of a transistor by comprising the channel layer with a first layer and a second layer with different carrier density and/or mobility. CONSTITUTION: A transistor includes a channel layer(C1), a source(S1), a drain(D1), and a gate(G1). The channel layer has different mobility and includes a lower layer(10) and an upper layer(20). The lower layer and the upper layer are made of the different oxide. The source and the drain are contacted with both sides of the channel layer. The gate applies the electric field to the channel layer. The closest layer to the gate among the lower layer and the upper layer determines the mobility of the transistor.
Abstract translation: 目的：提供沟道层和包括该沟道层的晶体管，以通过包括具有不同载流子密度和/或迁移率的第一层和第二层的沟道层来控制晶体管的阈值电压和迁移率。 构成：晶体管包括沟道层（C1），源极（S1），漏极（D1）和栅极（G1）。 沟道层具有不同的迁移率，并且包括下层（10）和上层（20）。 下层和上层由不同的氧化物制成。 源极和漏极与沟道层的两侧接触。 栅极将电场施加到沟道层。 下层和上层之间最靠近栅极的层决定了晶体管的迁移率。
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Patent Agency Ranking
公开(公告)号：KR1020100000650A
公开(公告)日：2010-01-06
申请号：KR1020080060228
申请日：2008-06-25
Applicant: 삼성전자주식회사
CPC classification number: H01L29/0665 , B82Y10/00 , H01L27/1214 , H01L29/0673 , H01L29/0676 , H01L29/7869 , H01L33/18 , H01L33/28
Abstract: PURPOSE: A display device using an oxide diode is provide to improve a life and light emitting efficiency by forming a plurality of nano rod diodes on a plug metal layer. CONSTITUTION: A display device includes a substrate, a thin film transistor layer(20), and a light emitting layer(30). The thin film transistor layer is formed on the substrate. The light emitting layer includes a plug metal layer(31), a plurality of nano rod diodes(34), and a transparent electrode(35). The plug metal layer is formed on the thin film transistor layer. The plurality of nano rod diodes are vertically formed on the plug metal layer. The transparent electrode is formed on the plurality of nano rod diodes. Each nano rod diode includes a lower layer part, an upper layer part, and a non-doped region.
Abstract translation: 目的：使用氧化二极管的显示装置用于通过在插塞金属层上形成多个纳米棒状二极管来提高寿命和发光效率。 构成：显示装置包括基板，薄膜晶体管层（20）和发光层（30）。 薄膜晶体管层形成在基板上。 发光层包括插塞金属层（31），多个纳米棒状二极管（34）和透明电极（35）。 插塞金属层形成在薄膜晶体管层上。 多个纳米棒状二极管垂直地形成在插塞金属层上。 透明电极形成在多个纳米棒状二极管上。 每个纳米棒二极管包括下层部分，上层部分和非掺杂区域。
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公开(公告)号：KR1020090131555A
公开(公告)日：2009-12-29
申请号：KR1020080057488
申请日：2008-06-18
Applicant: 삼성전자주식회사
CPC classification number: H03K19/01714
Abstract: PURPOSE: An inverter device and an operating method thereof are provided to perform a high operation speed by enhancing an output voltage through a first parasitic capacitance of a load transistor. CONSTITUTION: A first transistor(T10) applies a power voltage to a first drain(D1), and outputs an output voltage from a first source(S1). A second transistor(T20) applies an input voltage to a second gate(G2), and connects a second drain(D2) to the first source in order to output the output voltage. A third transistor(T30) applies a power voltage to a third gate and a third drain(D3), and connects a third source(S3) to the first gate. The first gate and the first source capacitively couple the first transistor.
Abstract translation: 目的：通过增加负载晶体管的第一寄生电容的输出电压，提供逆变器装置及其操作方法来执行高操作速度。 构成：第一晶体管（T10）将电源电压施加到第一漏极（D1），并输出来自第一源极（S1）的输出电压。 第二晶体管（T20）将输入电压施加到第二栅极（G2），并且将第二漏极（D2）连接到第一源极以输出输出电压。 第三晶体管（T30）将电源电压施加到第三栅极和第三漏极（D3），并将第三源极（S3）连接到第一栅极。 第一个栅极和第一个源极电容耦合第一个晶体管。
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公开(公告)号：KR1020090001368A
公开(公告)日：2009-01-08
申请号：KR1020070065684
申请日：2007-06-29
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/2436 , H01L27/2463
Abstract: The non-volatile semiconductor device is provided to reduce the size of the selecting transistor by forming the selecting transistor in the memory cells and the other layer and then the contact in the selecting transistor. The non-volatile semiconductor device comprises the semiconductor substrate(230), and a plurality of memory cells(WP1-WPn) formed on the semiconductor substrate. One or more selecting transistor(GSLP,SSLP) is formed on the semiconductor substrate. The selecting transistor is formed in the memory cells and the other layer. One or more selecting transistor comprises the first contact which connects the dataline or the power line to the selecting transistor and the second contact which connects the selecting transistor and memory cells. The first contact connects the dataline or the power line to the selecting transistor through the first doped region of the semiconductor substrate. One or more selecting transistor comprises the first selecting transistor and the second selection transistor.
Abstract translation: 提供非易失性半导体器件以通过在存储单元中形成选择晶体管，而在另一层中形成选择晶体管，然后在选择晶体管中形成接触来减小选择晶体管的尺寸。 非易失性半导体器件包括半导体衬底（230）和形成在半导体衬底上的多个存储单元（WP1-WPn）。 在半导体衬底上形成一个或多个选择晶体管（GSLP，SSLP）。 选择晶体管形成在存储单元和另一层中。 一个或多个选择晶体管包括将数据线或电源线连接到选择晶体管的第一触点和连接选择晶体管和存储单元的第二触点。 第一个触点通过半导体衬底的第一掺杂区将数据线或电源线连接到选择晶体管。 一个或多个选择晶体管包括第一选择晶体管和第二选择晶体管。
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公开(公告)号：KR1020080076608A
公开(公告)日：2008-08-20
申请号：KR1020070016778
申请日：2007-02-16
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/7869 , H01L29/78609
Abstract: A thin film transistor and a fabricating method thereof are provided to prevent a channel layer made of oxide semiconductor material from damaging and suppress a deterioration of property by covering a part of the channel layer with a protection layer. A thin film transistor comprises a channel layer(110), source and drain electrodes(130a,130b), a protection layer(120), a gate electrode(150), and a gate insulation layer(140). The channel is formed of an oxide semiconductor material. The source and drain electrode face each other on the channel layer. The protection layer covers the channel under the source and drain electrodes. The gate electrode applies an electric field to the channel layer. The gate insulation layer is disposed between the gate electrode and the channel layer. The channel layer is a ZnO based material layer. The channel layer a(In2O3), b(Ga2O3), and c(ZnO), wherein a, b, and c meets the terms of a>=0, b>=0, and c>0.
Abstract translation: 提供薄膜晶体管及其制造方法，以防止由氧化物半导体材料制成的沟道层损坏并通过用保护层覆盖沟道层的一部分来抑制性能的劣化。 薄膜晶体管包括沟道层（110），源极和漏极（130a，130b），保护层（120），栅极电极（150）和栅极绝缘层（140）。 通道由氧化物半导体材料形成。 源极和漏极在沟道层上彼此面对。 保护层覆盖源极和漏极下的沟道。 栅电极向沟道层施加电场。 栅极绝缘层设置在栅电极和沟道层之间。 沟道层是ZnO基材料层。 通道层a（In2O3），b（Ga2O3）和c（ZnO），其中a，b和c满足a> = 0，b> = 0和c> 0的项。
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公开(公告)号：KR100207618B1
公开(公告)日：1999-07-15
申请号：KR1019930018356
申请日：1993-09-13
Applicant: 삼성전자주식회사
IPC: H01M10/00
Abstract: 2차전지의 음극 제조방법 및 이를 갖는 2차전지가 개시된다. Ti+Ni을 적어도 40 원자% 이상 함유한 수소저장합금을 분쇄하고 기판상에 충전하는 단계를 포함하는 2차전지의 음극 제조방법에 있어서, 상기 수소저장합금을 700 내지 1350℃ 온도 범위에서 1 내지 80시간 동안 열처리하는 단계, 및 상기 열처리한 수소저장합금을 분쇄한 다음에 슬러리로 제조하여 기판상에 충전하고 압착하는 단계를 포함하는 2차전지의 음극 제조방법에 따라 제조된 음극을 갖는 2차전지의 내압 특성 및 내구성이 향상되고 급속충방전이 가능하게 된 우수한 것이다.
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