公开(公告)号：KR100421055B1

公开(公告)日：2004-03-04

申请号：KR1020020027442

申请日：2002-05-17

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  신홍재 ,  김재학 ,  이수근

IPC: H01L21/28

CPC classification number: H01L21/76808 ,  H01L21/76813 ,  H01L21/76835

Abstract: A method for forming a metal wiring layer in a semiconductor device using a dual damascene process is provided. A stopper layer, an interlayer insulating layer, and a hard mask layer are sequentially formed on a semiconductor substrate having a conductive layer. A first photoresist pattern that comprises a first opening having a first width is formed on the hard mask layer. The hard mask layer and portions of the interlayer insulating layer are etched using the first photoresist pattern as an etching mask, thereby forming a partial via hole having the first width. The first photoresist pattern is removed. An organic material layer is coated on the semiconductor substrate having the partial via hole is formed to fill the partial via hole with the organic material layer. A second photoresist pattern that comprises a second opening aligned with the partial via hole and having a second width greater than the first width is formed on the coated semiconductor substrate. The organic material layer and the hard mask layer on the interlayer insulating layer are etched using the second photoresist pattern as an etching mask. The second photoresist pattern and the organic material layer are simultaneously removed. A wiring region having the second width and a via hole having the first width are formed by etching the interlayer insulating layer using the hard mask layer as an etching mask.

Abstract translation: 提供了一种使用双镶嵌工艺在半导体器件中形成金属布线层的方法。 在具有导电层的半导体衬底上顺序形成阻挡层，层间绝缘层和硬掩模层。 在硬掩模层上形成包括具有第一宽度的第一开口的第一光致抗蚀剂图案。 使用第一光致抗蚀剂图案作为蚀刻掩模来蚀刻硬掩模层和层间绝缘层的部分，由此形成具有第一宽度的部分过孔。 第一光致抗蚀剂图案被去除。 将有机材料层涂覆在具有部分通孔的半导体基板上以形成部分通孔以填充有机材料层。 包括与部分通孔对齐的第二开口并具有大于第一宽度的第二宽度的第二光致抗蚀剂图案形成在涂覆的半导体基板上。 使用第二光致抗蚀剂图案作为蚀刻掩模来蚀刻层间绝缘层上的有机材料层和硬掩模层。 第二光致抗蚀剂图案和有机材料层同时被去除。 通过使用硬掩模层作为蚀刻掩模蚀刻层间绝缘层来形成具有第二宽度的布线区域和具有第一宽度的通孔。

公开(公告)号：KR100421039B1

公开(公告)日：2004-03-03

申请号：KR1020010023751

申请日：2001-05-02

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  신홍재 ,  이수근

IPC: H01L21/3065

Abstract: PURPOSE: A method and an apparatus for removing a photoresist formed on an interlayer dielectric of a semiconductor device are provided to maintain a dielectric constant of the interlayer dielectric after an ashing process is performed on the photoresist formed on the interlayer dielectric. CONSTITUTION: An interlayer dielectric of a low dielectric constant is formed on a surface of a semiconductor substrate(S1). A photoresist is coated on an upper portion of the interlayer dielectric(S2). A contact hole is formed by patterning the photoresist and the interlayer dielectric(S3). The photoresist is removed by performing an ashing process for the photoresist and the interlayer dielectric is exposed thereby(S4). The interlayer dielectric is contacted with activated hydrogen by performing an activated hydrogen process(S5). A post-process such as a stripping process is performed(S6). The interlayer dielectric is formed by an SiOC:H-based compound. The activated hydrogen includes hydrogen plasma.

Abstract translation: 目的：提供一种去除形成在半导体器件的层间介质上的光刻胶的方法和设备，以在对形成在层间介质上的光刻胶执行灰化处理之后保持层间介质的介电常数。 构成：在半导体基板（S1）的表面形成低介电常数的层间绝缘膜。 光致抗蚀剂被涂覆在层间电介质（S2）的上部。 通过图案化光致抗蚀剂和层间电介质来形成接触孔（S3）。 通过对光致抗蚀剂进行灰化处理来去除光致抗蚀剂，并且由此暴露层间电介质（S4）。 通过执行活化氢过程（S5）使层间电介质与活化氢接触。 执行诸如剥离处理的后处理（S6）。 层间电介质由SiOC：H基化合物形成。 活化的氢包括氢等离子体。

公开(公告)号：KR1020040010130A

公开(公告)日：2004-01-31

申请号：KR1020030044852

申请日：2003-07-03

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  이수근 ,  박완재 ,  김재학

IPC: H01L21/28

CPC classification number: H01L21/76808

Abstract: PURPOSE: A method for fabricating a dual damascene wire of a microelectronic device using a hybrid type low-k dielectric material and a carbonless organic filling material is provided to prevent the delay of an RC signal and restrict the interference between signals and the increase of power consumption by forming an interlayer dielectric with the low-k dielectric material. CONSTITUTION: A hybrid type insulating layer(130) having a dielectric constant below 3.3 is formed on a substrate(100). A via(150) is formed within the hybrid type insulating layer(130). The via(150) is filled by a carbonless organic filling material(160). A trench(190) is formed by etching the carbonless organic filling material(160) and the hybrid type insulating layer(130). The remaining carbonless organic filling material is removed from the via(150). A wire is formed by filling up a wire material into the trench(190) and the via(150).

Abstract translation: 目的：提供一种使用混合型低k介电材料和无碳有机填充材料制造微电子器件的双镶嵌线的方法，以防止RC信号的延迟并限制信号之间的干扰和功率的增加 通过与低k电介质材料形成层间电介质来消耗。 构成：在基板（100）上形成介电常数低于3.3的混合型绝缘层（130）。 在混合型绝缘层（130）内形成通孔（150）。 通孔（150）由无碳有机填充材料（160）填充。 通过蚀刻无碳有机填充材料（160）和混合型绝缘层（130）形成沟槽（190）。 剩余的无碳有机填充材料从通孔（150）中除去。 通过将线材填充到沟槽（190）和通孔（150）中而形成导线。

公开(公告)号：KR1020020092681A

公开(公告)日：2002-12-12

申请号：KR1020010031455

申请日：2001-06-05

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  신홍재 ,  김재학 ,  이수근

IPC: H01L21/28

Abstract: PURPOSE: A method for manufacturing a semiconductor device using dual damascene technology is provided to prevent an over-etch of a lower interconnection by using an etch stopping layer composed of an N-doped SiC layer. CONSTITUTION: An etch stopping layer(23) and an interlayer dielectric(26) are sequentially formed on a semiconductor substrate(100) having a lower conductive layer(20). A via hole(30) is formed to expose the etch stopping layer(23) by selectively etching the interlayer dielectric. A second photoresist pattern(32) is formed to expose portions of the interlayer dielectric(26) on the resultant structure. At this time, a photoresist residue(34) is remaining in the via hole. A groove(36) is formed by etching the exposed interlayer dielectric(26) using the second photoresist pattern(32) and the photoresist residue(34) as a mask. After removing the second photoresist pattern(32) and the photoresist residue(34), the surface of the lower conductive layer(20) is exposed by removing the exposed etch stopping layer(23). An N-doped SiC layer is used as the etch stopping layer(23).

Abstract translation: 目的：提供一种使用双镶嵌技术制造半导体器件的方法，以通过使用由N掺杂的SiC层构成的蚀刻停止层来防止下部互连的过度蚀刻。 构成：在具有下导电层（20）的半导体衬底（100）上依次形成蚀刻停止层（23）和层间电介质（26）。 通孔（30）形成为通过选择性地蚀刻层间电介质来露出蚀刻停止层（23）。 形成第二光致抗蚀剂图案（32）以暴露所得结构上的层间电介质（26）的部分。 此时，通孔中残留有光致抗蚀剂残留物（34）。 通过使用第二光致抗蚀剂图案（32）和光致抗蚀剂残留物（34）作为掩模蚀刻暴露的层间电介质（26）来形成凹槽（36）。 在去除第二光致抗蚀剂图案（32）和光致抗蚀剂残留物（34）之后，通过去除暴露的蚀刻停止层（23）来暴露下导电层（20）的表面。 使用N掺杂的SiC层作为蚀刻停止层（23）。

公开(公告)号：KR100341483B1

公开(公告)日：2002-06-21

申请号：KR1019990054706

申请日：1999-12-03

Applicant: 삼성전자주식회사

Inventor： 김선래 ,  이수근 ,  박선후

IPC: H01L21/316

CPC classification number: H01L21/76837 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76897

Abstract: 고밀도플라즈마산화막에의한갭 매립방법이개시되어있다. 기판상에형성된패턴들사이의갭을산화막으로매립하는반도체장치의제조방법에있어서, 갭을포함한기판의상부에제1 고밀도플라즈마산화막층을증착하는제1 단계; 불소(F) 이온을이용하여제1 고밀도플라즈마산화막층을소정두께만큼식각하는제2 단계; 그리고결과물의상부에제2 고밀도플라즈마산화막층을증착하는제3 단계에의해갭을매립하는것을특징으로한다. 불소이온에의해제1 고밀도플라즈마산화막층을식각하여갭의어스펙트비를감소시킨후 제2 고밀도플라즈마산화막층을증착함으로써, 보이드가없는갭 매립을구현할수 있다.

公开(公告)号：KR1020020010832A

公开(公告)日：2002-02-06

申请号：KR1020000044327

申请日：2000-07-31

Applicant: 삼성전자주식회사

Inventor： 이수근

IPC: H01L21/28

Abstract: PURPOSE: A method for manufacturing a dual damascene is provided to reduce the thickness of photoresist used as an etch mask for forming a via pattern, by forming an anti-reflective coating(ARC) along the bending of an interconnection pattern. CONSTITUTION: An interlayer dielectric is formed on a substrate(200) where an electrical active region(201) is buried. The first photoresist pattern exposing the upper portion of the electrical active region is formed on the interlayer dielectric. A part of the ARC(206) and the interlayer dielectric is etched to form the interconnection pattern by using the first photoresist pattern as an etch mask. The first photoresist pattern is eliminated. An ARC is formed on the resultant structure having the interconnection pattern. The second photoresist pattern opening a part of the groove of the interconnection pattern is formed on the ARC. The interlayer dielectric is etched to form a via pattern reaching the electrical active region by using the second photoresist pattern as an etch mask. The second photoresist pattern is removed. The groove of the interconnection pattern and the via pattern formed by the abovementioned process is filled with a metal material.

Abstract translation: 目的：提供一种用于制造双镶嵌的方法，以通过沿着互连图案的弯曲形成抗反射涂层（ARC）来减小用作形成通孔图案的蚀刻掩模的光致抗蚀剂的厚度。 构成：在埋设有电活性区域（201）的基板（200）上形成层间电介质。 暴露电活性区域的上部的第一光致抗蚀剂图案形成在层间电介质上。 通过使用第一光致抗蚀剂图案作为蚀刻掩模，蚀刻ARC（206）和层间电介质的一部分以形成互连图案。 消除了第一光致抗蚀剂图案。 在具有互连图案的合成结构上形成ARC。 在ARC上形成打开互连图形的槽的一部分的第二光致抗蚀剂图案。 通过使用第二光致抗蚀剂图案作为蚀刻掩模，蚀刻层间电介质以形成到达有源区域的通孔图案。 去除第二光致抗蚀剂图案。 通过上述工艺形成的互连图案的凹槽和通孔图案填充有金属材料。

公开(公告)号：KR1020010104964A

公开(公告)日：2001-11-28

申请号：KR1020000026443

申请日：2000-05-17

Applicant: 삼성전자주식회사

Inventor： 이수근

IPC: C04B35/565

CPC classification number: C04B35/565 ,  C04B2235/6581 ,  C04B2235/6586

Abstract: 낮은 유전상수를 갖는 비정질 실리콘 카바이드 조성물 및 그 형성방법이 제공된다. 이 조성물은 규소(Si), 탄소(C), 수소(H) 및 질소(N)를 포함하되, 질소의 조성비는 규소, 탄소, 수소 및 질소의 총원자량을 기준으로 2 내지 10 원자량(atomic )이고, Si-CH
3 결합 및 Si-C 결합을 포함한다. 이 조성물을 형성하기 위한 방법은 밀폐된 공정챔버 내의 척 상에 반도체기판을 로딩시키는 단계와, 공정챔버 내의 압력을 대기압보다 낮은 저압으로 조절함과 동시에 척의 온도를 300℃ 내지 450℃의 온도로 조절하는 단계와, 공정챔버 내부로 트라이 메틸 사일레인(tri-methyl-silane; SiH(CH
3 )
3 ) 가스와 같은 전구체(precursor) 및 운송가스(carrier gas)로서 질소가스를 주입함과 동시에 공정챔버 내의 전극에 플라즈마 소스로서 라디오 주파수 전원을 인가하여, 반도체기판 상에 비정질 실리콘 카바이드막을 형성하는 단계를 포함한다.

公开(公告)号：KR100295782B1

公开(公告)日：2001-07-12

申请号：KR1019990026765

申请日：1999-07-03

Applicant: 삼성전자주식회사

Inventor： 이승재 ,  이수근 ,  임훈

IPC: H01L21/76

CPC classification number: H01L21/76229

Abstract: 반도체장치의얕은트렌치소자분리의형성방법이개시되어있다. 반도체기판의상부에액티브마스크층을형성한다. 액티브마스크층및 기판을식각하여다수의트렌치들을형성한다. 액티브마스크층의상부및 트렌치들의내부에트렌치의깊이보다크고트렌치의깊이에액티브마스크층의두께를더한값보다작은두께로고밀도플라즈마산화막층을증착한다. 고밀도플라즈마산화막층의상부에테트라에틸오소실리케이트(TEOS)를소오스로하여플라즈마방식으로캡핑산화막층을증착한다. 액티브마스크층의표면이노출될때까지캡핑산화막층및 고밀도플라즈마산화막층을연마한다. 트랜지스터의 Idoff 특성을개선하고, 보이드없이트렌치를충전할수 있다.

公开(公告)号：KR1020010055527A

公开(公告)日：2001-07-04

申请号：KR1019990056743

申请日：1999-12-10

Applicant: 삼성전자주식회사

Inventor： 박지순 ,  이수근 ,  박선후

IPC: H01L21/28

Abstract: PURPOSE: A method for forming copper wiring layer is provided to prevent a lifting phenomenon of a dielectric layer during a chemical mechanical polishing(CMP) process by performing on Argon(Ar) sputter etching in-situ after forming a copper wiring layer and before a dielectric layer is formed with a nitride, eliminating entirely an oxide layer grown on the surface of a copper wiring layer and improving an adhesive strength between the copper wiring layer and the dielectric layer deposited thereon. CONSTITUTION: A process forms a copper wiring layer on the top of a semiconductor substrate. The process eliminates an oxide layer is grown on the surface of the copper wiring layer by using an Argon(Ar) sputter etching. The process deposits a dielectric layer on the results. The Argon(Ar) sputter etching is performed on the depositing of the dielectric layer. After the Argon(Ar) sputter etching, the process further includes an ammonia(NH3) plasma treatment processing on the surface of the copper wiring layer.

Abstract translation: 目的：提供一种形成铜布线层的方法，以在化学机械抛光（CMP）工艺中通过在形成铜布线层之后在原位进行氩（Ar）溅射蚀刻，并且在 电介质层由氮化物形成，完全消除了在铜布线层的表面上生长的氧化物层，并且提高了铜布线层和沉积在铜布线层之间的电介质层之间的粘合强度。 构成：工艺在半导体衬底的顶部形成铜布线层。 该工艺消除了通过氩（Ar）溅射蚀刻在铜布线层的表面上生长氧化物层。 该过程在结果上沉积介电层。 对沉积介电层进行氩（Ar）溅射蚀刻。 在氩（Ar）溅射蚀刻之后，该工艺还包括在铜布线层的表面上的氨（NH 3）等离子体处理处理。

公开(公告)号：KR1020010025923A

公开(公告)日：2001-04-06

申请号：KR1019990036988

申请日：1999-09-01

Applicant: 삼성전자주식회사

Inventor： 이승재 ,  이수근 ,  박선후

IPC: H01L21/76

Abstract: PURPOSE: A shallow trench isolation method is provided to prevent a nitride layer liner from being clipped and to embody a good gap filling of a high density plasma oxide layer, by making an upper corner portion of a trench not broken and have a good profile. CONSTITUTION: A pad oxide layer(102) and a nitride layer(104) are sequentially formed on a semiconductor substrate(100). The nitride layer, the pad oxide layer and the semiconductor substrate are etched to form a trench(108). A nitride layer liner(112) is deposited on the resultant structure. A high density plasma oxide layer(114) is firstly deposited on the resultant structure to bury a part of the trench. A high density plasma oxide layer is secondly deposited to completely bury the trench. A D/S ratio is not less than 5.9 in the first deposition step of the high density plasma oxide layer(DS ratio is (deposition rate+sputtering etch rate)/(sputtering etch rate)).

Abstract translation: 目的：提供浅沟槽隔离方法，以防止氮化物层衬垫被夹住，并通过使沟槽的上角部分不破裂并具有良好的外形来体现高密度等离子体氧化物层的良好间隙填充。 构成：衬垫氧化物层（102）和氮化物层（104）依次形成在半导体衬底（100）上。 蚀刻氮化物层，衬垫氧化物层和半导体衬底以形成沟槽（108）。 在所得结构上沉积氮化物层衬垫（112）。 首先在所得结构上沉积高密度等离子体氧化物层（114）以埋入沟槽的一部分。 第二次沉积高密度等离子体氧化物层以完全掩埋沟槽。 在高密度等离子体氧化物层的第一沉积步骤（DS比率（沉积速率+溅射蚀刻速率）/（溅射蚀刻速率））中，D / S比不小于5.9。