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公开(公告)号：KR1019950011965B1
公开(公告)日：1995-10-12
申请号：KR1019920002485
申请日：1992-02-19
Applicant: 삼성전자주식회사
IPC: G11C16/00
CPC classification number: G11C16/12
Abstract: a memory cell array consiting of a number of memory cells; a row decoder responsive to row address signals for selectively activating a selected one of row lines; a data input buffer for receiving program data; a number of column selecting MOS transistors each having a gate electrode, a first electrode connected to a respective one of the bit lines and a second electrode connected to the data line; a column decoder having a number of outputs connected to the gate electrode of respective ones of the column selecting MOS transistors; a number of program voltage generating circuits each of which is selectively operable for generating a program voltage output with a first or second logic level; a number of first selecting MOS transistors having a first electrode connected to the program voltage output of respective ones of the program voltage generating circuits; a number of second selecting MOS transistors having a first electrode connected to the program voltage output of the respective ones of the program voltage generating circuits; and a select circuit having a first output connected to the gate electrode of each of the first selecting MOS transistors and a second output connected to the gate electrode of each of the second selecting MOS transistors.
Abstract translation: 由多个存储单元组成的存储单元阵列; 响应于行地址信号的行解码器，用于选择性地激活所选行的一行行; 用于接收节目数据的数据输入缓冲器; 多个列选择MOS晶体管，每个具有栅电极，连接到相应一个位线的第一电极和连接到数据线的第二电极; 列解码器，其具有连接到列选择MOS晶体管的各个栅极的输出数量; 多个编程电压产生电路，每个程序电压产生电路选择性地可操作地用于产生具有第一或第二逻辑电平的编程电压输出; 多个第一选择MOS晶体管，其具有连接到各个编程电压产生电路的编程电压输出的第一电极; 多个第二选择MOS晶体管，其具有连接到各个编程电压产生电路的编程电压输出的第一电极; 以及选择电路，其具有连接到每个第一选择MOS晶体管的栅极的第一输出和连接到每个第二选择MOS晶体管的栅电极的第二输出。
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公开(公告)号：KR1019940010106A
公开(公告)日：1994-05-24
申请号：KR1019920018437
申请日：1992-10-08
Applicant: 삼성전자주식회사
IPC: G11C11/41
Abstract: 본 발명은 반도체 메모리 장치에서 특히 스태틱 램의 전류센스앰프를 소정의 액티브동작시 프리세팅(presetting)하는 전류 센스 앰프 회로에 관한 것으로, 전류센스앰프의 프리세팅을 위하여 전류센스앰프의 양단을 등화시키고 또한 전류센스앰프의 프리세팅을 위하여 전류센스앰프에 연결된 비트라인 또는 데이타 라인을 소정의 정전압레벨로 프리차아지하므로서, 신뢰성 높고 라이트 리커버리 특성이 우사한 전류센스앰프를 제공할 수 있어서, 전류센싱회로가 특히 라이트 리커버리에 민감하게 반응하는 것을 개설할 뿐만 아니라 쎌 데이타의 액세스를 고속화시키는 효과가 있다.
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Patent Agency Ranking
公开(公告)号：KR1019930005027A
公开(公告)日：1993-03-23
申请号：KR1019910014272
申请日：1991-08-19
Applicant: 삼성전자주식회사
IPC: G11C11/407
Abstract: 내용 없음.
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公开(公告)号：KR1019910002748B1
公开(公告)日：1991-05-04
申请号：KR1019880004120
申请日：1988-04-12
Applicant: 삼성전자주식회사
CPC classification number: G11C7/1057 , G11C7/1051 , H03K19/0013 , H03K19/09429
Abstract: A data output buffer circuit for reducing the real access time by precharging the data bus comprises an inverting means for inverting the data of the sense amplifying output terminal (SAS,SAS'), a logic means for producing the driving control signal, an output driver means for driving the output using the driving control signal and a precharge driver means, controlled by the address shift detection signal of the data, for rapidly precharging the output data bus.
Abstract translation: 用于通过预充电数据总线来减少实际访问时间的数据输出缓冲器电路包括用于反相感测放大输出端（SAS，SAS'）的数据的反相装置，用于产生驱动控制信号的逻辑装置，输出驱动器 用于使用驱动控制信号驱动输出的装置和由数据的地址移位检测信号控制的预充电驱动器装置，用于快速预充电输出数据总线。
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公开(公告)号：KR1019890001847B1
公开(公告)日：1989-05-25
申请号：KR1019860003537
申请日：1986-05-07
Applicant: 삼성전자주식회사
IPC: H01L27/00
CPC classification number: G11C29/785
Abstract: The circuit replaces the normal line connected to a defective normal memory cell with redundant line connected to normal memory cell on a selected address signal. The circuit includes a normal decoder, an address signal generator for selecting normal memory cell connected to normal line and a redundant decoder having 1 address signal added program.
Abstract translation: 该电路用连接到所选择的地址信号上的正常存储器单元的冗余线路连接到有缺陷的普通存储器单元的法线。 该电路包括正常解码器，用于选择连接到法线的正常存储器单元的地址信号发生器和具有1个地址信号相加程序的冗余解码器。
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