公开(公告)号：KR1019990002519A

公开(公告)日：1999-01-15

申请号：KR1019970026139

申请日：1997-06-20

Applicant: 삼성전자주식회사

Inventor： 한정희

IPC: H01L21/28

Abstract: 순수 구리를 이용한 금속 배선의 형성 방법이 개시되어 있다. 반도체 기판의 상부에 장벽 금속층을 형성한 후, 그 위에 감광막 패턴을 형성하여 금속 배선이 형성될 부위를 오픈시킨다. 상기 반도체 기판을 구리 수용액에 담근 후 전기 도금을 실시하여 상기 오픈된 부위에 구리 배선층을 형성한다. 구리 수용액 속에서 장벽 금속층을 이용한 전기 도금 방법을 사용하여 순수 구리 배선층을 형성함으로써, 배선 공정을 용이하게 진행할 수 있다.

公开(公告)号：KR101759926B1

公开(公告)日：2017-07-21

申请号：KR1020090121107

申请日：2009-12-08

Applicant: 삼성전자주식회사 ,  더 리전츠 오브 더 유니버시티 오브 캘리포니아

Inventor： 김지영 ,  왕캉엘 ,  박용직 ,  한정희 ,  홍진우

IPC: H01L29/786 ,  H01L21/28

CPC classification number: H01L2924/0002 ,  H01L2924/00

Abstract: 메모리반도체장치, 그제조방법및 동작방법을제공한다. 이장치는기판의상부면에수직한장축을가지면서 2차원적으로배열되는반도체패턴들및 반도체패턴들을가로지르는장축을가지면서반도체패턴들사이에서 3차원적으로배열되는워드라인들을포함할수 있다.

Abstract translation: 存储器半导体器件及其制造方法和操作方法。 该器件可以包括具有垂直于衬底的垂直轴二维布置的半导体图案，以及三维布置在具有与半导体图案交叉的长轴的半导体图案之间的字线。

公开(公告)号：KR1020100132433A

公开(公告)日：2010-12-17

申请号：KR1020100034764

申请日：2010-04-15

Applicant: 삼성전자주식회사 ,  더 리전츠 오브 더 유니버시티 오브 캘리포니아

Inventor： 김지영 ,  왕캉엘 ,  박용직 ,  한정희 ,  홍진우

IPC: H01L21/8247

CPC classification number: H01L27/11578 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: PURPOSE: A semiconductor device and a method for manufacturing the same are provided to increase the integrity of a NAND type flash memory device by controlling an electric connection between a bit-line and a source-ling using a voltage applied to gate-lines. CONSTITUTION: One or more upper wirings are arranged on a lower wiring. A plurality of gate-lines(70) successively stacked to from a gate structure. The gate structure is arranged between the upper wiring and the lower wiring. A semiconductor pattern(55) connects the upper wirings and the lower wirings. The semiconductor pattern includes horizontal parts(HP) and a vertical part(VP). The horizontal parts are in parallel with the upper side of a substrate(10). The vertical part connects the horizontal parts.

Abstract translation: 目的：提供半导体器件及其制造方法，以通过使用施加到栅极线的电压来控制位线和源极之间的电连接来增加NAND型闪存器件的完整性。 构成：一个或多个上布线布置在下布线上。 从栅极结构依次层叠的多个栅极线（70）。 栅极结构布置在上部布线和下部布线之间。 半导体图案（55）连接上部布线和下部布线。 半导体图案包括水平部分（HP）和垂直部分（VP）。 水平部分与衬底（10）的上侧平行。 垂直部分连接水平部分。

公开(公告)号：KR1020100084213A

公开(公告)日：2010-07-26

申请号：KR1020090003565

申请日：2009-01-16

Applicant: 삼성전자주식회사

Inventor： 한정희 ,  정경인 ,  차화진 ,  배은희 ,  도미선

IPC: H04W36/32

Abstract: PURPOSE: A method and a device for estimating moving speed of a terminal in a wireless communication system are provided to accurately estimate moving speed of a terminal. CONSTITUTION: When a UE(User Equipment) moves to a cell controlled by another ENB(Evolved Node B) of a wireless communication system, a cell size information transmitting unit(501) transmits size information of cells to which the UE moves during a set period and a cell controlled by the ENB to another ENB. A terminal speed estimating unit(502) estimates moving speed of the UE using size information of the cell. A transmission power measuring unit(504) measures transmission power of a downlink signal transmitted to a cell coverage edge of the ENB.

Abstract translation: 目的：提供一种用于估计无线通信系统中的终端的移动速度的方法和装置，以准确估计终端的移动速度。 构成：当UE（用户设备）移动到由无线通信系统的另一个ENB（演进节点B）控制的小区时，小区尺寸信息发送单元（501）在一组中发送UE移动的小区的大小信息 期间和由ENB控制的另一个ENB的电池。 终端速度估计单元（502）使用小区的大小信息来估计UE的移动速度。 发送功率测量单元（504）测量发送到ENB的小区覆盖边缘的下行链路信号的发送功率。

公开(公告)号：KR1020100083236A

公开(公告)日：2010-07-22

申请号：KR1020090002524

申请日：2009-01-13

Applicant: 삼성전자주식회사

Inventor： 한정희 ,  차화진

IPC: H04W36/24 ,  H04W36/08

CPC classification number: H04W36/245 ,  H04W36/0061

Abstract: PURPOSE: A handover apparatus and a method thereof are provided to prevent that unnecessary handover is performed about at least a cell among the cells performing the handover. CONSTITUTION: In case a terminal performs handover to a target cell, a controller(200) transmits handover information received from the terminal and an adjacent cell to the target cell. In case of confirming that the terminal performs the handover to a plurality of cells while moving an overlapped cell coverage region, a parameter correcting unit(206) modifies a handover parameter of the target cell. The parameter correcting unit prevents that unnecessary handover process is generated.

Abstract translation: 目的：提供切换装置及其方法，以防止执行切换的小区中的至少一个小区执行不必要的切换。 构成：在终端对目标小区进行切换的情况下，控制器（200）将从终端接收的切换信息和相邻小区发送到目标小区。 在确认终端在移动重叠小区覆盖区域的同时进行到多个小区的切换的情况下，参数校正单元（206）修改目标小区的切换参数。 参数校正单元防止产生不必要的切换过程。

公开(公告)号：KR1020090062613A

公开(公告)日：2009-06-17

申请号：KR1020070129965

申请日：2007-12-13

Applicant: 삼성전자주식회사

Inventor： 박찬진 ,  황현상 ,  최혜정 ,  김정우 ,  채수두 ,  한정희 ,  박호경

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/66833

Abstract: A nonvolatile memory device and a method for manufacturing the same are provided to obtain uniform distribution by using a silicon nitride film including the metal as a charge trap layer. A gate structure(20) is formed on a semiconductor substrate(10). The gate structure is comprised of a tunnel dielectric layer, a charge trap layer, a blocking dielectric layer and a gate electrode. A source/drain region(12) is formed within the semiconductor substrate of both sides of the gate structure. The charge trap layer is comprised of the nitride film including the metal. The metal is selected among the transition metal. The rate of the transition metal is within the range of 1 to 50% not to lose a nonconductor characteristic of the nitride film. The charge trap layer is made of a titanium silicon nitride film or the tantalum silicon nitride film.

Abstract translation: 提供一种非易失性存储器件及其制造方法，以通过使用包含该金属的氮化硅膜作为电荷陷阱层来获得均匀的分布。 在半导体衬底（10）上形成栅极结构（20）。 栅极结构由隧道介电层，电荷陷阱层，阻挡电介质层和栅电极构成。 源极/漏极区域（12）形成在栅极结构的两侧的半导体衬底内。 电荷陷阱层由包括金属的氮化物膜构成。 在过渡金属中选择金属。 过渡金属的比例在1〜50％的范围内，不会损失氮化膜的非导体特性。 电荷陷阱层由氮化硅钛膜或氮化钽膜制成。

公开(公告)号：KR100855990B1

公开(公告)日：2008-09-02

申请号：KR1020070030047

申请日：2007-03-27

Applicant: 삼성전자주식회사 ,  리전츠 오브 더 유니버시티 오브 캘리포니아

Inventor： 한정희 ,  김지영 ,  왕강롱 ,  김정우 ,  채수두 ,  박찬진

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/115 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L21/76224

Abstract: A non-volatile memory device and a manufacturing method thereof are provided to increase integration degree by forming a stack structure instead of a plane structure. A plurality of semiconductor layers(120) are laminated on a substrate(105). A plurality of second semiconductor layers(115) are inserted between the first semiconductor layers. The second semiconductor layers are recessed from one end of the first semiconductor layers in order to define a plurality of first trenches. A plurality of first storage nodes(140a) are formed on surfaces of the second semiconductor layers in the first trenches. A plurality of first control gate electrodes(150a) are formed on the first storage nodes in order to fill up the first trenches.

Abstract translation: 提供非易失性存储器件及其制造方法，以通过形成堆叠结构而不是平面结构来提高积分度。 多个半导体层（120）层叠在基板（105）上。 多个第二半导体层（115）插入在第一半导体层之间。 第二半导体层从第一半导体层的一端凹入以限定多个第一沟槽。 多个第一存储节点（140a）形成在第一沟槽中的第二半导体层的表面上。 在第一存储节点上形成多个第一控制栅电极（150a），以便填充第一沟槽。

公开(公告)号：KR1020080051014A

公开(公告)日：2008-06-10

申请号：KR1020070095665

申请日：2007-09-20

Applicant: 삼성전자주식회사

Inventor： 박병국 ,  박일한 ,  채수두 ,  김정우 ,  한정희 ,  박찬진

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/2463 ,  H01L27/2436 ,  H01L27/2481

Abstract: An AND-type and NOR-type flash memory arrays, a manufacturing method thereof and an operating method thereof are provided to form plural same silicon pins having certain width and height on an upper portion of a substrate. A local bit line(LBL1) is connected to bit lines(BL1,BL2,BLn) via a first select transistor(ST11). Memory cells(M11 to Mm1) are connected in parallel to the local bit line and the local source line. A local source line(LSL1) is commonly connected to a source of the respective memory cells, and a common source line(CSL) is connected to the local source line via a second select transistor(ST21). A drain select line(DSL) and a source select line(SSL) are electrically connected to a gate of the first select transistor and a gate of the second select transistor. Plural word lines(WL1 to WLm) are connected to a gate of each memory cell. The local bit line and the local source line have a first doped layer and a second doped layer which are vertically spaced apart from silicon pins.

Abstract translation: 提供AND型和NOR型闪速存储器阵列，其制造方法和操作方法，以在衬底的上部上形成具有一定宽度和高度的多个相同的硅销。 局部位线（LBL1）经由第一选择晶体管（ST11）连接到位线（BL1，BL2，BLn）。 存储单元（M11〜Mm1）与本地位线和本地源极线并联连接。 本地源极线（LSL1）通常连接到各个存储单元的源极，并且公共源极线（CSL）经由第二选择晶体管连接到本地源极线（ST21）。 漏极选择线（DSL）和源选择线（SSL）电连接到第一选择晶体管的栅极和第二选择晶体管的栅极。 多个字线（WL1至WLm）连接到每个存储单元的栅极。 局部位线和局部源极线具有与硅引脚垂直间隔开的第一掺杂层和第二掺杂层。

公开(公告)号：KR100750195B1

公开(公告)日：2007-08-17

申请号：KR1020060091972

申请日：2006-09-21

Applicant: 삼성전자주식회사

Inventor： 채수두 ,  김정우 ,  박찬진 ,  한정희

IPC: H01L27/115 ,  H01L21/8247

公开(公告)号：KR100688521B1

公开(公告)日：2007-03-02

申请号：KR1020050004455

申请日：2005-01-18

Applicant: 삼성전자주식회사

Inventor： 전상훈 ,  최성규 ,  김정우 ,  황현상 ,  한정희 ,  최상무 ,  박성호

IPC: H01L29/78

CPC classification number: H01L21/02148 ,  H01L21/02156 ,  H01L21/02159 ,  H01L21/28282 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/792

Abstract: 본 발명은 고유전율 절연막을 포함하는 반도체 메모리 소자 및 그 제조 방법에 관한 것이다. 반도체 기판에 각각 형성된 제 1불순물 영역 및 제 2불순물 영역; 상기 반도체 기판 상에 상기 제 1불순물 영역 및 상기 제 2불순물 영역과 각각 접하며 형성되며 Hf Silicate, Zr Silicate, Y Silicate 또는 란탄 계열 금속 Silicate 중 적어도 어느 하나의 물질을 포함하여 ((Hf, Zr, Y or Ln)O
2 )
x (SiO
2 )
1-x (0.03≤x≤0.26)의 조성을 지닌 절연막; 및 상기 절연막 상에 형성된 게이트 전극층;을 포함하는 고유전률 절연막을 포함하는 반도체 메모리 소자 및 그 제조 방법을 제공한다.