公开(公告)号：KR1019950009635B1

公开(公告)日：1995-08-25

申请号：KR1019920023353

申请日：1992-12-04

Applicant: 한국전자통신연구원

Inventor： 이성재 ,  박경완 ,  김경옥

IPC: H01L39/00

Abstract: depositing a Mo-C film(20) on an insulation substrate(10) by sputtering Mo at the room temperature under the mixture gas atmosphere of argon, acetylene and methane gases; forming an insulation film(30) on the MO-C film(20) using the defined resist pattern; and forming gate source and electrodes(40G, 40D, 40S) by lift-off process. The obtained transistor is a swiching device using a superconductor. The method reduces noise and electric power consumption.

Abstract translation: 在氩气，乙炔和甲烷气体的混合气体气氛下，在室温下溅射Mo，在绝缘基板（10）上沉积Mo-C膜（20） 使用限定的抗蚀图案在MO-C膜（20）上形成绝缘膜（30）; 以及通过剥离工艺形成栅极源极和电极（40G，40D，40S）。 所获得的晶体管是使用超导体的swiching器件。 该方法降低了噪声和功耗。

公开(公告)号：KR100087213B1

公开(公告)日：1995-07-24

申请号：KR1019920011451

申请日：1992-06-29

Applicant: 한국전자통신연구원

Inventor： 이성재 ,  박경완 ,  박경호

IPC: H01L39/00

公开(公告)号：KR1019940012675A

公开(公告)日：1994-06-24

申请号：KR1019920020985

申请日：1992-11-10

Applicant: 한국전자통신연구원

Inventor： 이성재 ,  박경완 ,  박경호 ,  장순호

IPC: H01L29/80

Abstract: 본 발명은 GaAs/AlGaAs 2차원 전자기체층을 조셉슨 접합부분으로 사용하고 AlGaAs층 위에 게이트를 부착시킴으로써, 소스와 드레인 사이의 초전도 전류(supercurrent)를 효과적으로 제어하는 조셉슨 FET(Field Effect Transistor)에 관한 것이다.

公开(公告)号：KR1020040031933A

公开(公告)日：2004-04-14

申请号：KR1020020061073

申请日：2002-10-07

Applicant: 한국전자통신연구원

Inventor： 이성재 ,  박경완 ,  조원주 ,  장문규 ,  정우석

IPC: H01L21/027 ,  B82Y40/00

CPC classification number: H01L21/32137 ,  H01L21/3065

Abstract: PURPOSE: A dry lithography method and a method for forming a gate pattern using the same are provided to be capable of being replaced as a conventional lithography method without using a dry process. CONSTITUTION: A pattern printing object layer is prepared(S100). At this time, the pattern printing object layer is made of silicon. An electron beam irradiation is partially performed on the pattern printing object layer(S110). The pattern printing object layer is selectively removed by carrying out an RIE(Reactive Ion Etching) process using the etching rate difference between the electron beam irradiated portion and the electron beam free portion of the pattern printing object layer(S120). Preferably, the RIE process is carried out while heating the pattern printing object layer at the range of 0-1000 °C.

Abstract translation: 目的：提供干式光刻方法和使用其形成栅极图案的方法，以便能够在不使用干法的情况下作为常规光刻方法进行替换。 构成：制作图案印刷对象层（S100）。 此时，图案印刷对象层由硅制成。 在图案印刷对象层上部分地进行电子束照射（S110）。 通过使用电子束照射部分和图案印刷对象层的电子束自由部分之间的蚀刻速率差进行RIE（反应离子蚀刻）处理，选择性地除去图案印刷对象层（S120）。 优选地，在0-1000℃的范围内加热图案印刷对象层的同时进行RIE处理。

公开(公告)号：KR100425582B1

公开(公告)日：2004-04-06

申请号：KR1020010073006

申请日：2001-11-22

Applicant: 한국전자통신연구원

Inventor： 이성재 ,  조원주 ,  박경완

IPC: H01L21/334

CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/7833

Abstract: A method of fabricating a MOS transistor having shallow source/drain junction regions is provided. A diffusion source layer is formed on a semiconductor substrate on which gate patterns are formed. Same type or different type of impurities are implanted into the diffusion source layer several times in different directions. As a result, dislocation does not occur and the impurity concentration of the diffusion source layer can be nonuniformly controlled so that damage to the crystal structure of the semiconductor substrate does not occur. Also, the impurities nonuniformly contained in the diffusion source layer are diffused into the semiconductor substrate by a solid phase diffusion method to form shallow source/drain junction regions having LDD regions and highly doped source/drain regions by a self-alignment method.

Abstract translation: 提供了一种制造具有浅源极/漏极结区的MOS晶体管的方法。 在其上形成有栅极图案的半导体衬底上形成扩散源层。 相同类型或不同类型的杂质以不同方向被多次注入到扩散源层中。 结果，不发生位错，并且可以不均匀地控制扩散源层的杂质浓度，从而不会发生对半导体衬底的晶体结构的损害。 此外，扩散源层中不均匀包含的杂质通过固相扩散方法扩散到半导体衬底中，以通过自对准方法形成具有LDD区域和高度掺杂的源极/漏极区域的浅源极/漏极结区域。

公开(公告)号：KR1020040015417A

公开(公告)日：2004-02-19

申请号：KR1020020047506

申请日：2002-08-12

Applicant: 한국전자통신연구원

Inventor： 장문규 ,  이성재 ,  정우석 ,  조원주 ,  박경완

IPC: H01L27/12

CPC classification number: H01L29/42384 ,  H01L29/458 ,  H01L29/7839 ,  H01L29/78609 ,  H01L29/78696

Abstract: PURPOSE: A SBTT(Schottky Barrier Tunnel Transistor) using a thin SOI(Silicon On Insulator) layer and a manufacturing method thereof are provided to be capable of restraining short channel effect and preventing leakage current. CONSTITUTION: A SBTT is provided with a substrate(110) and a buried oxide layer(120) formed on the substrate. At this time, a groove portion is formed on the buried oxide layer. The SBTT further includes a thin SOI layer(130) formed across the upper portion of the groove portion, an insulating layer for enclosing the SOI layer, a gate(150a) formed at the upper portion of the insulating layer, and a source/drain region(160) formed at both sidewalls of the gate. At this time, the source/drain region are made of a silicide layer. Preferably, the groove portion is filled with a conductive layer(150b).

Abstract translation: 目的：使用薄SOI（绝缘体上硅）层的SBTT（肖特基势垒隧道晶体管）及其制造方法能够抑制短沟道效应并防止漏电流。 构成：SBTT设置有形成在基板上的基板（110）和掩埋氧化物层（120）。 此时，在掩埋氧化物层上形成槽部。 SBTT还包括横跨沟槽部分的上部形成的薄SOI层（130），用于封装SOI层的绝缘层，形成在绝缘层上部的栅极（150a），以及源极/漏极 形成在栅极的两个侧壁处的区域（160）。 此时源/漏区由硅化物层制成。 优选地，沟槽部分填充有导电层（150b）。

公开(公告)号：KR1020040014716A

公开(公告)日：2004-02-18

申请号：KR1020020047348

申请日：2002-08-10

Applicant: 한국전자통신연구원

Inventor： 심규환 ,  송영주 ,  김상훈 ,  강진영 ,  박경완

IPC: H01L29/737

Abstract: PURPOSE: A method for fabricating a semiconductor device having an oxide layer formed on a bottom of an active region is provided to fabricate easily an SOI device by using an oxidation period difference between a silicon germanium layer and a silicon layer. CONSTITUTION: A buffer layer(300) of a silicon germanium layer is grown on an upper surface of a semiconductor substrate(100). An active layer(400) of a silicon layer is formed on an upper surface of the buffer layer(300). An isolation layer(500) is formed by oxidizing selectively the active layer(400). An oxide layer(370) of the buffer layer(300) is formed on a bottom of the active layer(400) by oxidizing selectively the buffer layer(300) under the isolation layer(500).

Abstract translation: 目的：提供一种制造半导体器件的方法，该半导体器件具有形成在有源区的底部上的氧化物层，以通过使用硅锗层和硅层之间的氧化周期差容易地制造SOI器件。 构成：在半导体衬底（100）的上表面上生长硅锗层的缓冲层（300）。 在缓冲层（300）的上表面上形成硅层的有源层（400）。 通过有选择地氧化有源层（400）来形成隔离层（500）。 缓冲层（300）的氧化物层（370）通过选择性地氧化隔离层（500）下的缓冲层（300）而形成在有源层（400）的底部上。

公开(公告)号：KR1020020042956A

公开(公告)日：2002-06-08

申请号：KR1020000072320

申请日：2000-12-01

Applicant: 한국전자통신연구원

Inventor： 하정숙 ,  박경완 ,  박승민 ,  고영조

IPC: H01L21/203

CPC classification number: C23C14/0652 ,  C23C14/28 ,  C30B23/002 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02581 ,  H01L21/0259 ,  H01L21/02631 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31116 ,  H01L29/167

Abstract: PURPOSE: A method for forming an erbium-doped silicon nano dot is provided to prevent contamination by vaporizing a solid target within a reactor and change doping density by controlling intensity of laser beam. CONSTITUTION: A silicon substrate(11) is located in an inside of a reaction chamber(10) in order to maintain a state of vacuum. A pulsed light source portion is located at an outside of the reaction chamber(10) in order to a pulsed light beam(21). A plurality of target rotation portion(40a,40b) is located in the inside of the reaction chamber(10) in order to load a plurality of target(30a,30b) and rotate the targets(30a,30b). A light beam splitter(50) is used for splitting the pulsed light beam(21) into a plurality of light beam(22a,22b). A plurality of light beam intensity control portion(60a,60b) is used for controlling the intensity of the light beams(22a,22b). A plurality of polarization portion(70a,70b) is used for polarizing the light beams(22a,22b).

Abstract translation: 目的：提供一种形成铒掺杂硅纳米点的方法，以防止通过在反应器内汽化固体靶而产生污染，并通过控制激光束的强度来改变掺杂密度。 构成：为了保持真空状态，硅衬底（11）位于反应室（10）的内部。 脉冲光源部分位于反应室（10）的外侧，以便于脉冲光束（21）。 多个目标旋转部（40a，40b）位于反应室（10）的内部，以装载多个靶（30a，30b）并使靶（30a，30b）旋转。 光束分离器（50）用于将脉冲光束（21）分成多个光束（22a，22b）。 多个光束强度控制部（60a，60b）用于控制光束（22a，22b）的强度。 多个偏振部分（70a，70b）用于偏振光束（22a，22b）。

公开(公告)号：KR1020010048131A

公开(公告)日：2001-06-15

申请号：KR1019990052682

申请日：1999-11-25

Applicant: 한국전자통신연구원

Inventor： 이성재 ,  박경완 ,  신민철

IPC: H01L29/732

CPC classification number: B82Y10/00 ,  G11C2216/08 ,  H01L29/7613 ,  H01L49/006 ,  Y10S438/962 ,  Y10S977/937

Abstract: PURPOSE: A single electron device is provided to promote the realization of a single electron device including the wiring by managing its tunnel junction part with etching and the structure of bottle neck on the basis of a simplified process of photolithography and etch using the ultra thin metal film. CONSTITUTION: A semiconductor substrate has an ultra thin metal film. An electron island is formed between a source and a drain formed on the ultra thin metal film. The weak links has a predetermined thickness from the boundary when etching to thereby guide a coulomb closure of the electron island in the form of a bottle neck to play the role of tunnel junction connecting the source to the electronic island, and the island to the drain. A gate electrode is capacitively coupled with the electron island by being formed at a predetermined interval around the electron island.

Abstract translation: 目的：提供单电子器件，通过在简化的光刻工艺和使用超薄金属的蚀刻的基础上，通过用蚀刻和瓶颈的结构管理其隧道结部分来促进包括布线在内的单个电子器件的实现 电影。 构成：半导体衬底具有超薄金属膜。 在形成在超薄金属膜上的源极和漏极之间形成电子岛。 薄弱环节在蚀刻时具有从边界预定的厚度，从而以瓶颈的形式引导电子岛的库仑封闭，以发挥将源连接到电子岛的隧道结，以及岛到漏极 。 通过以电子岛周围的预定间隔形成栅电极与电子岛电容耦合。

公开(公告)号：KR100149888B1

公开(公告)日：1999-03-20

申请号：KR1019940022873

申请日：1994-09-10

Applicant: 한국전자통신연구원

Inventor： 이성재 ,  박경완 ,  신민철

IPC: H01L27/10 ,  B82Y40/00

Abstract: 본 발명은 절연막이 형성된 소정의 기판 위에 금속 초박막을 주재료로 하여 가공(사진 식각, 재증착, 열처리 등)시킨 능동소자를 형성한 이차원 집적회로 구조와, 이를 한 단위로 하여 이들을 동일 기판 위에 연속적으로 적층하여 삼차원화시킨 금속박막으로 구성된 전자소자의 삼차원 집적회로에 관한 것이다.
본 발명은 한 단위구조의 집적회로만으로도 반도체를 재료로 한 소자에 비해 훨씬 높은 집적도를 얻을 수 있을 뿐만 아니라, 이 단위구조들을 동일 기판 위에 적층하여 삼차원화 할 수 있기 때문에 적층의 개수만큼 집적도가 배가될 수 있다.