公开(公告)号：KR100470832B1

公开(公告)日：2005-03-10

申请号：KR1020020047506

申请日：2002-08-12

Applicant: 한국전자통신연구원

Inventor： 장문규 ,  이성재 ,  정우석 ,  조원주 ,  박경완

IPC: H01L27/12

CPC classification number: H01L29/42384 ,  H01L29/458 ,  H01L29/7839 ,  H01L29/78609 ,  H01L29/78696

Abstract: 쇼트키 장벽 관통 트랜지스터 및 그 제조방법에 관한 것이다. 본 발명에 따른 쇼트키 장벽 관통 트랜지스터는, 기계적인 지지를 위한 기판층 위에 형성되면서 상면에 홈을 가지는 매립 절연 산화막을 포함하고, 매우 얇은 SOI(Silicon On Insulator)층이 홈 위를 가로지른다. 절연막이 홈 위 SOI층 부분을 둘러싸며, 그 절연막 위에는 홈보다 넓게 게이트가 형성되어 있다. 게이트 양측에는 실리사이드로 이루어진 소오스/드레인이 위치하며, 홈은 도전막으로 채워져 있다. 본 발명에 따르면, SOI층의 두께를 최소화하여 누설전류가 최소화되고, 게이트 아래의 SOI층 안에 형성되는 채널이 게이트와 도전막으로 완전히 둘러싸인 구조이므로 동작특성이 개선된다.

公开(公告)号：KR1020010055920A

公开(公告)日：2001-07-04

申请号：KR1019990057255

申请日：1999-12-13

Applicant: 한국전자통신연구원

Inventor： 김성복 ,  노정래 ,  박경완

IPC: H01S5/32

Abstract: PURPOSE: A manufacturing method for quantum dot laser diode is provided to make manufacturing process simple by forming at the same time current interception structure and activity area by using the difference with a lattice structure of an epitaxial layer formed on upper part. CONSTITUTION: The first stage of a current interception structure forms the first cladding layer(22) of the first challenge type on substrates of the challenge type. The second stage makes a quantum dot glow up on the upper part of the first cladding layer(22). The third stage forms current interception layer to oxidize the first cladding layer(22), using the quantum dot activity layer(23) for oxidation mask. The firth stage forms the second cladding layer(25) of the second challenge type on the quantum dot activity layer(23) including the current interception layer. The fifth stage forms cap layer of challenge type on the second cladding layer(25) upper part. The first stage of a manufacturing method of quantum dot laser diode forms the first cladding layer(22) on the semiconductor board of first challenge type. The second stage forms voluntary the quantum dot activity layer of 3 dimension island type. The third stage forms current interception layer by oxidizing the first cladding layer with using the quantum dot activity layer(23) as the oxidation mask. The firth stage forms the second cladding layer(25) of the second challenge type with a lot of a lattice defect on upper part of the current interception layer.

Abstract translation: 目的：提供量子点激光二极管的制造方法，通过使用与上部形成的外延层的晶格结构的差异，同时形成电流截止结构和活性区域，使制造工艺简单。 构成：电流截取结构的第一阶段在挑战型的衬底上形成第一挑战类型的第一覆层（22）。 第二阶段使第一包层（22）的上部的量子点发光。 第三阶段使用量子点活性层（23）形成氧化掩模，形成电流截取层以氧化第一包层（22）。 细长阶段在包括电流截取层的量子点活动层（23）上形成第二挑战类型的第二包层（25）。 第五阶段在第二包层（25）上部形成挑战类型的帽层。 量子点激光二极管的制造方法的第一阶段在第一挑战型半导体板上形成第一覆层（22）。 第二阶段形成自主的三维岛型量子点活动层。 第三级通过使用量子点活性层（23）作为氧化掩模来氧化第一包层形成电流截止层。 细长阶段形成第二挑战类型的第二包层（25），在当前截取层的上部形成大量的格子缺陷。

公开(公告)号：KR1020010054538A

公开(公告)日：2001-07-02

申请号：KR1019990055387

申请日：1999-12-07

Applicant: 한국전자통신연구원

Inventor： 노정래 ,  김성복 ,  박경완

IPC: H01L21/20

CPC classification number: H01L29/127 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02546

Abstract: PURPOSE: A fabrication method of a compound semiconductor device with self-aligned growth of self-assembled quantum dots and a current blocking structure is provided to enhance uniformity in size of the quantum dots and to simplify control of position at a substrate plane. CONSTITUTION: The method includes forming a tilted superlattice substrate in which a GaAs layer(12) and an AlAs layer are formed with a step-terrace structure on a compound semiconductor substrate(10), then forming an aluminum oxide layer(13) by oxidizing the AlAs layer, then selectively forming InAs quantum dots(14) on the GaAs layer(12) by using a Stranski-Krastanow growth mode, and then forming a crystalline GaAs layer(15) on the GaAs layer(12) and also forming an amorphous GaAs layer(16) on the aluminum oxide layer(13). Since growth of the InAs quantum dots(14) is limited to the GaAs layer(12), the quantum dots(14) have a uniform size. In addition, the amorphous GaAs layer(16) can be utilized as the current blocking structure.

Abstract translation: 目的：提供具有自组装量子点和电流阻挡结构的自对准生长的化合物半导体器件的制造方法，以增强量子点尺寸的均匀性并简化对衬底平面位置的控制。 构成：该方法包括：在化合物半导体衬底（10）上形成有梯级结构的GaAs层（12）和AlAs层的倾斜超晶格衬底，然后通过氧化形成氧化铝层（13） AlAs层，然后通过使用Stranski-Krastanow生长模式在GaAs层（12）上选择性地形成InAs量子点（14），然后在GaAs层（12）上形成结晶GaAs层（15），并且还形成 在氧化铝层（13）上的非晶GaAs层（16）。 由于InAs量子点（14）的生长被限制到GaAs层（12），所以量子点（14）具有均匀的尺寸。 此外，非晶GaAs层（16）可以用作电流阻挡结构。

公开(公告)号：KR1020000037780A

公开(公告)日：2000-07-05

申请号：KR1019980052529

申请日：1998-12-02

Applicant: 한국전자통신연구원

Inventor： 노정래 ,  김성복 ,  박경완

IPC: H01L21/82

CPC classification number: B82Y10/00 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02513 ,  H01L21/02516 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02614 ,  H01L29/127 ,  Y10S438/962

Abstract: PURPOSE: A method for fabricating a semiconductor substrate is provided to fabricate a quantum dot structure in a simple manner without using an e-beam lithography apparatus. CONSTITUTION: A plurality of dielectric thin film patterns(2) are formed on a semiconductor substrate(1). A buffer layer(3) and a barrier layer(4) in a form of a pyramid are sequentially formed on the exposed semiconductor substrate(1). A Ga droplet(5) is formed at each barrier layer(4). The Ga droplet(5) is transformed into a GaAs quantum dot(6). Then, the semiconductor substrate(1) is subjected to a heat treatment process for a quantum effect. After that, a protecting layer(7) for surrounding the GaAs quantum dot(6) is formed on the semiconductor substrate(1).

Abstract translation: 目的：提供一种用于制造半导体衬底的方法，以简单的方式制造量子点结构，而不使用电子束光刻设备。 构成：在半导体衬底（1）上形成多个电介质薄膜图案（2）。 在暴露的半导体衬底（1）上依次形成呈锥体形式的缓冲层（3）和阻挡层（4）。 在每个阻挡层（4）处形成Ga液滴（5）。 Ga液滴（5）被转换成GaAs量子点（6）。 然后，对半导体基板（1）进行量子效应的热处理工序。 之后，在半导体衬底（1）上形成用于包围GaAs量子点（6）的保护层（7）。

公开(公告)号：KR100261462B1

公开(公告)日：2000-07-01

申请号：KR1019970046102

申请日：1997-09-08

Applicant: 한국전자통신연구원

Inventor： 박경완 ,  이성재 ,  신민철

IPC: H01L29/00

Abstract: PURPOSE: A multi-channel switching device using single electron tunneling is provided to reduce the number of unit devices by using conductivity according to each electric potential of electron islands. CONSTITUTION: A multi-channel switching device using single electron tunneling comprises a multitude of electron island and a conductive line. The multitude of electron island is arranged in a linear shape. Electrons of the electron island are isolated. The conductive line is penetrated into both directions of each electron island to a vertical direction of the arranged direction. The penetrating current is applied to a few electron island of a whole structure of the electron island arrangement.

Abstract translation: 目的：提供使用单电子隧穿的多通道开关器件，以根据电子岛的每个电位使用电导率来减少单元器件的数量。 构成：使用单电子隧穿的多通道开关器件包括多个电子岛和导电线。 大量的电子岛布置成线形。 分离电子岛的电子。 导电线沿着排列方向的垂直方向贯穿各电子岛的两个方向。 穿透电流被施加到电子岛布置的整个结构的几个电子岛。

公开(公告)号：KR100261270B1

公开(公告)日：2000-07-01

申请号：KR1019970059535

申请日：1997-11-12

Applicant: 한국전자통신연구원

Inventor： 박경완 ,  신민철 ,  이성재 ,  박문호 ,  오상철

IPC: H01L29/775 ,  B82Y10/00

Abstract: PURPOSE: A multi-function device involving a quantum dot array loop structure with multiple coulomb gaps is provided to reduce the size of the device for high integrity, and save consumption power by using very low operation current. CONSTITUTION: The plurality of quantum dots(1,2,...,N) are arrayed by a tunnel bonding to form the quantum dot array loop(30). A source(10) and a drain(20) are connected to two quantum dots of the plurality of quantum dots(1,2,...,N) by the tunnel bonding. Electrons are movable between respective quantum dots(1,2,...,N) by the tunnel bonding. In this structure, the voltage drop between the source(10) and drain(20) is applied to the array loop(30) and drain(20) because the charge capacitance between the drain(20) and quantum dot array loop(30) is much smaller than that between the source(10) and quantum dot array loop(30).

Abstract translation: 目的：提供一种涉及具有多个库仑间隙的量子点阵列环路结构的多功能设备，以减小高度完整性的器件尺寸，并通过使用非常低的工作电流来节省功耗。 构成：多个量子点（1,2，...，N）通过隧道结合排列以形成量子点阵列环（30）。 源极（10）和漏极（20）通过隧道结合连接到多个量子点（1,2，...，N）中的两个量子点。 电子通过隧道结合在各个量子点（1,2，...，N）之间移动。 在这种结构中，源极（10）和漏极（20）之间的电压降被施加到阵列环（30）和漏极（20），因为漏极（20）和量子点阵列环（30）之间的电荷电容 远小于源（10）和量子点阵列环（30）之间的距离。

公开(公告)号：KR1020000032310A

公开(公告)日：2000-06-15

申请号：KR1019980048732

申请日：1998-11-13

Applicant: 한국전자통신연구원

Inventor： 이성재 ,  박경완 ,  신민철 ,  박문호

IPC: H03F3/06

Abstract: PURPOSE: An output terminal amplification circuit for a single-electron circuit and quantum electrons circuit is provided to strengthen output impedance of current consisted of quantum electron demagnetization with the dozens level, and to isolate outside circuit thereby effectively preventing the single-electron circuit from noises. CONSTITUTION: An output terminal amplification circuit for a single electron circuit and quantum electrons circuit comprises the parts of: a single electron transistor(31) in which a gate is connected through a capacitor to output terminal of a memory circuit or a logic circuit with a large source impedance, consisted of a single electron or quantum electrons; an FET transistor(50) in which a gate is connected to source part of the above single electron transistor.

Abstract translation: 目的：提供用于单电子电路和量子电子电路的输出端子放大电路，以加强由数十级的量子电子去磁组成的电流的输出阻抗，并隔离外部电路，从而有效防止单电子电路的噪声 。 构成：用于单电子电路和量子电子电路的输出端子放大电路包括以下部分：单电子晶体管（31），其中栅极通过电容器连接到存储器电路的输出端或逻辑电路 大源阻抗由单电子或量子电子组成; 其中栅极连接到上述单电子晶体管的源极部分的FET晶体管（50）。

公开(公告)号：KR100258096B1

公开(公告)日：2000-06-01

申请号：KR1019970065066

申请日：1997-12-01

Applicant: 한국전자통신연구원

Inventor： 박경완 ,  신민철 ,  이성재 ,  박문호 ,  오상철

IPC: H01L21/20

CPC classification number: H01L21/76262

Abstract: PURPOSE: A method for manufacturing an SOI substrate is provided to achieve the SOI substrate formed with a silicon layer having a low impurity density with uniform thickness. CONSTITUTION: A mixing layer(12) including SiO2 and silicon is formed on a glass substrate(10) in an oxygen atmosphere by using an epitaxial device. At this time, the pressure of oxygen is gradually decreased. A silicon layer(14) is formed on the mixing layer(12) of SiO2 and silicon in a high vacuum state. At this time, the pressure of oxygen becomes zero. The mixing layer(12) of SiO2 and silicon is made of a nonconductor. The density of SiO2 is reduced and the density of silicon is increased in an upper portion of the glass substrate(10).

Abstract translation: 目的：提供一种用于制造SOI衬底的方法，以实现具有均匀厚度的具有低杂质密度的硅层形成的SOI衬底。 构成：通过使用外延装置，在氧气氛中的玻璃基板（10）上形成包括SiO 2和硅的混合层（12）。 此时，氧气的压力逐渐降低。 在高真空状态的SiO 2和硅的混合层（12）上形成硅层（14）。 此时，氧气的压力变为零。 SiO 2和硅的混合层（12）由非导体制成。 SiO 2的密度降低，硅的密度在玻璃基板（10）的上部增加。

公开(公告)号：KR100233833B1

公开(公告)日：1999-12-01

申请号：KR1019960048947

申请日：1996-10-28

Applicant: 한국전자통신연구원

Inventor： 박경완 ,  이성재 ,  신민철

IPC: H01L29/772

CPC classification number: B82Y10/00 ,  H01L29/66446 ,  H01L29/66977 ,  H01L29/772 ,  Y10S438/962

Abstract: 본 발명은 여러개의 온/오프(on/off) 상태를 갖는 다기능 트랜지스터 소자를 제작하기 위해 전자의 회절성을 2차원 전자 기체에 구현하는 것으로, 특히 전자의 통로에 반사 회절 그레이팅(grating) 모양의 구조를 삽입함으로써, 전자의 회절현상을 이용하여 드레인 전류의 크기를 조절하고, 여러개의 온/오프 상태를 갖는 양자 회절 트랜지스터 및 그 제조 방법에 관한 것이다.

公开(公告)号：KR1019990046907A

公开(公告)日：1999-07-05

申请号：KR1019970065066

申请日：1997-12-01

Applicant: 한국전자통신연구원

Inventor： 박경완 ,  신민철 ,  이성재 ,  박문호 ,  오상철

IPC: H01L21/20

Abstract: 본 발명은 산화물 기판을 사용하여 산소의 분위기내에서 실리콘을 원재료로 하는 분자선 단결정 제조기법을 이용하여 산화물을 균일하게 성장시킨 다음, 계속하여 산소 분위기의 압력을 점차로 줄여감에 따라 산화물과 실리콘의 혼합계면을 성장시킨 후, 그 혼합 계면위에 계속하여 실리콘 분자선 단결정 제조 기법을 이용하여 일정 두께의 실리콘 단결정을 성장하므로써 실리콘층이 매우 균일하고 불순물의 농도가 작은 SOI 기판을 제조한다.