公开(公告)号：KR100368323B1

公开(公告)日：2003-01-24

申请号：KR1019990025142

申请日：1999-06-29

Applicant: 한국전자통신연구원

Inventor： 오대곤 ,  남은수 ,  편광의

IPC: H01S5/30

Abstract: PURPOSE: A method for manufacturing a gain-combined single mode semiconductor laser is provided to manufacture a single mode laser light source by epi-layer growth once. CONSTITUTION: A method for manufacturing a gain-combined with single mode semiconductor laser has following steps. An active layer(12) is formed on a substrate(13). The active layer(12) has a quantum wire(8) structure. A clad layer(11) is formed is formed on the active layer(12). A resistive electrode contact layer(10) is formed on the clad layer. A stripe electrode is formed in order to generate laser-resonator in a perpendicular direction to the quantum wire(8) on the resistive electrode contact layer(10), thereby manufacture a single mode laser light source by one crystal growth.

Abstract translation: 目的：提供一种用于制造增益组合单模半导体激光器的方法，以通过一次外延层生长来制造单模激光源。 构成：一种制造与单模半导体激光器组合的增益的方法具有以下步骤。 有源层（12）形成在衬底（13）上。 有源层（12）具有量子线（8）结构。 在有源层（12）上形成包覆层（11）。 电阻电极接触层（10）形成在包层上。 形成条形电极以便在与电阻性电极接触层（10）上的量子线（8）垂直的方向上产生激光谐振腔，由此通过一次晶体生长来制造单模激光源。

公开(公告)号：KR100324203B1

公开(公告)日：2002-02-16

申请号：KR1019990040255

申请日：1999-09-18

Applicant: 한국전자통신연구원

Inventor： 조호성 ,  박경현 ,  편광의

IPC: H01S5/30

Abstract: 본발명은순수이득결합분포궤환형반도체레이저및 그제조방법에관한것이다. 본발명은반도체기판상에결정성장된활성층, 완충층, 회절격자가형성된이득결합층및 클래드층을포함하여수직구조를이루는이득결합형분포궤환반도체레이저에있어서, 활성층보다밴드갭에너지가낮은이득결합층에회절격자를형성한 후, 격자사이를굴절률보상층으로메워기존의회절격자구조를변화시킴으로써, 회절격자가형성되어주기적인광이득/손실을주는이득결합층에서발생하는굴절률변조를굴절률보상층으로상쇄시킨다. 따라서본 발명의이득결합분포궤환형반도체레이저는단일모드수율이높을뿐만아니라높은측모드억제율특성을갖는다.

公开(公告)号：KR100290460B1

公开(公告)日：2001-06-01

申请号：KR1019970072065

申请日：1997-12-22

Applicant: 한국전자통신연구원

Inventor： 이창석 ,  강성원 ,  김민건 ,  이재진 ,  편광의

IPC: H03F3/45

Abstract: PURPOSE: A differential amplifier circuit is provided to easily remove various mixed frequency components from original differential signal by inputting signal with a source electrode and outputting signal with a drain electrode. CONSTITUTION: A differential amplifier circuit comprises a first load resistance, a second load resistance, a first transistor(22) and a second transistor(23). The first load resistance is connected with a power voltage distribution line(21) and a first output terminal. The second load resistance is connected with the distribution line and a second output terminal. In the first transistor, a drain electrode is connected with the first output terminal and the first signal is inputted through a source electrode, and the second signal is inputted through a gate. In the second transistor, a drain electrode is connected with a second output terminal and the second signal is inputted through the source electrode, and the first signal is inputted through the gate. The first signal is of reverse phase to that of the second signal.

公开(公告)号：KR100281636B1

公开(公告)日：2001-06-01

申请号：KR1019970070307

申请日：1997-12-19

Applicant: 한국전자통신연구원

Inventor： 이진희 ,  박병선 ,  윤형섭 ,  박철순 ,  편광의

IPC: H01L21/306

Abstract: 본 발명은 균일하고 제어성이 좋은 뒷면 via- hole 을 제조하는 제조 방법을 제공하기 위한 것이다. 본 발명은, 소자 및 회로 기판(1)에는 활성층(2)와 전면 금속층(3)으로 주로 구성되어 있고, 표면에 보호막을 입혀, 고온 왁스(4)로 투명 지지 기판(5)에 접착 하고 , 비아-홀 영역(10a)과 창 영역(10b)이 있는 마스크(10)를 사용하여, 감광막(8)의 표면에 패턴을 형성하고, Ni금속을 증착한 후 리프트 오프 공정으로 Ni 보조 마스크(9)를 형성하고, 모니터용 창(11)을 만든다. 그 위에 다시 감광막을 입히고, 비아-홀 용 마스크(10)을 사용하여 비아홀 식각용 패턴(12)과, 식각 모니터용 창(11a)을 형성 하고, 비아홀용 감광막 마스크(12)와 Ni금속 마스크(9)를 사용하여 식각함으로써, 식각된 비아-홀부분(13)과 식각된 비아-홀 창(14), (14a), (14b)을 형성한다. 그리고, 식각 마스크인 감광막 및 Ni 금속 마스크를 제거하고, 베이스 금속(15)를 증착하여 전기 도금 방법으로 금(15), (15a)를 도금하며, 이후, 투명 지지대(5)를 탈착하고 세척을 하여 완료한다. 따라서, 본 발명에 의하면, 창을 사용하여 비아-홀의 식각 완료점을 정확하게 찾아내고 2회의 리소그라피 공정을 사용하여 뒷면 비아-홀의 마스크를 안정함으로서, 웨이퍼 내에서 균일하고 재현성 있는 뒷면 비아-홀을 얻을 수 있게 된다.

公开(公告)号：KR1020010028165A

公开(公告)日：2001-04-06

申请号：KR1019990040255

申请日：1999-09-18

Applicant: 한국전자통신연구원

Inventor： 조호성 ,  박경현 ,  편광의

IPC: H01S5/30

Abstract: PURPOSE: A pure gain bond distributed feedback laser diode and a production method thereof are provided to give high mode yield of sun light wavelength and high inhibition of lateral mode, and have good operation property. CONSTITUTION: A distributed feedback laser diode consists of substrate(10), active layer(11), buffer layer(12), gain bond layer(13) and clad layer(14). The layers form perpendicular structure. A diffraction lattice is formed on the gain bond which is disposed adjacent to the active layer. A refractive index compensation layer is filled between diffraction lattices of the gain bond layer, modifying the existing diffraction lattice. Thus diffraction lattice is formed to offset the refractive index alteration by the refractive index compensate layer. A production method comprises growing active layer, buffer layer and gain bond layer on the semiconductor substrate, forming a diffraction lattice on the gain bond layer using laser holography, filling the removed part with the refractive index compensate layer after etching, and re-growing clad layer.

Abstract translation: 目的：提供纯增益键分布式反馈激光二极管及其制造方法，以提供太阳光波长的高模量产量和高横向模式的抑制，并具有良好的操作性能。 构成：分布式反馈激光二极管由衬底（10），有源层（11），缓冲层（12），增益接合层（13）和覆层（14）组成。 层形成垂直结构。 在与活性层相邻设置的增益接合上形成衍射晶格。 在增益接合层的衍射晶格之间填充折射率补偿层，修改现有的衍射晶格。 因此，形成衍射晶格以抵消折射率补偿层的折射率变化。 一种制造方法包括在半导体衬底上生长有源层，缓冲层和增益接合层，在激光全息术的增益接合层上形成衍射晶格，在蚀刻之后用折射率补偿层填充去除的部分， 层。

公开(公告)号：KR100276077B1

公开(公告)日：2001-01-15

申请号：KR1019980016753

申请日：1998-05-11

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 이진희 ,  박병선 ,  윤형섭 ,  맹성재 ,  박철순 ,  편광의

IPC: H01L29/12

Abstract: PURPOSE: A method for forming a fine T-shaped gate electrode is provided to reduce leakage current of a gate by forming a fine gate having a long leg. CONSTITUTION: An ohmic metallic layer(4) is formed by growing an active layer(2) and a cap layer(3) on a substrate(1). The first insulating layer(5) is formed thereon. The first resist and the second resist are applied on the first insulating layer(5). A head pattern and a leg pattern of a T-shaped gate are by exposing and developing the first resist and the second resist. A length of the gate is controlled by forming the second insulating layer on the gate pattern. A part of the first insulating layer(5) located on the gate leg pattern is etched by using an amorphous etch method. A multi-gate recess process is performed. A gate metal(12) is deposited by using an electron beam. A T-shaped gate(12) is formed by performing a lift-off process.

Abstract translation: 目的：提供一种用于形成精细T形栅电极的方法，以通过形成具有长支脚的细门来减小栅极的漏电流。 构成：通过在衬底（1）上生长活性层（2）和覆盖层（3）来形成欧姆金属层（4）。 第一绝缘层（5）形成在其上。 将第一抗蚀剂和第二抗蚀剂施加在第一绝缘层（5）上。 通过使第一抗蚀剂和第二抗蚀剂曝光和显影，T形门的头部图案和腿部图案。 通过在栅极图案上形成第二绝缘层来控制栅极的长度。 通过使用非晶蚀刻方法蚀刻位于栅极腿图案上的第一绝缘层（5）的一部分。 执行多栅极凹槽工艺。 通过使用电子束沉积栅极金属（12）。 通过执行剥离过程形成T形门（12）。

公开(公告)号：KR100274153B1

公开(公告)日：2000-12-15

申请号：KR1019970071617

申请日：1997-12-22

Applicant: 한국전자통신연구원

Inventor： 박병선 ,  윤형섭 ,  이진희 ,  박철순 ,  편광의

IPC: H01L21/328

Abstract: PURPOSE: A manufacturing method of microscopic T-type gate with supporter is provided to make a T-type gate metal easily for improving a transistor characteristic. CONSTITUTION: The first metal layer(3) is vaporized and patterned on a substrate(1) with a channel layer. An ohmic layer(2) is evaporated and patterned as a T-type for building a T-type gate. After being doped and etched a PMMA(Poly-Methyl MethAcrylate) resist and an MMA-MMA(Methyl MethAcrylate-Methyl MethAcrylate) resist respectively, the leg and the head of a T-type gate is formed, and a T-type gate pattern is built. The part of exposed substrate(1) is recessed, and an insulating layer(6) is attached on the sidewall of the resist layers and flattened layer with the same thickness of the resist layers using plasma CVD(Chemical Vapor Deposition) method. Using dry etching method, the insulating layer(6) is etched selectively for building a supporter. After recessing the exposed substrate(1), a gate metal is doped and the resist layers are removed by soaking in acetone or in solvent. Then, the T-type gate metal(7) is produced.

Abstract translation: 目的：提供具有支撑体的微观T型栅极的制造方法，以便容易地制造T型栅极金属以改善晶体管特性。 构成：第一金属层（3）被蒸发并在具有通道层的基板（1）上图案化。 欧姆层（2）被蒸发并图案化为用于构建T型浇口的T型。 在分别掺杂并蚀刻了PMMA（聚甲基丙烯酸甲酯）抗蚀剂和MMA-MMA（甲基丙烯酸甲酯 - 甲基丙烯酸甲酯）抗蚀剂后，形成T型栅极的支脚和头部，并且形成T型栅极图案 建成 暴露的基板（1）的一部分凹陷，并且使用等离子体CVD（化学气相沉积）方法，在抗蚀剂层的侧壁和具有相同厚度的抗蚀剂层的平坦层上附着绝缘层（6）。 使用干蚀刻方法，绝缘层（6）被选择性地蚀刻以构建支撑体。 在暴露的衬底（1）凹陷之后，掺杂栅极金属，并通过浸入丙酮或溶剂中去除抗蚀剂层。 然后，制造T型栅极金属（7）。

公开(公告)号：KR100261461B1

公开(公告)日：2000-07-01

申请号：KR1019970071083

申请日：1997-12-19

Applicant: 한국전자통신연구원

Inventor： 윤형섭 ,  이진희 ,  박병선 ,  박철순 ,  편광의

IPC: H01L29/80

Abstract: PURPOSE: A method for manufacturing a compound semiconductor device is provided to improve the high frequency characteristic of the compound semiconductor device by forming an asymmetric recess structure. CONSTITUTION: An epitaxial substrate is formed by sequentially stacking a buffer layer(13), a channel layer(14), a spacer layer(15), a doping layer(16), a short key layer(17), a low density doping layer(18), the first etch stop layer(19), the first ohmic layer(20), the second etch stop layer and the second ohmic layer(22) on a semi-insulating substrate(12). After forming a photoresist pattern for forming an ohmic electrode, an ohmic metal layer is formed and an ohmic electrode of a source/drain is formed by performing a heat-treating process. Then, the first and second stepped gate recess structures are sequentially formed by using a gate recess method. The low density doping layer(18) is selectively etched to form the third asymmetric gate structure. Then, a Ti/Pt/Au gate metal electrode(31) is deposited on the structure. After that, a photoresist pattern is removed by using a lift off method so as to form a field effect type compound semiconductor device.

Abstract translation: 目的：提供一种制造化合物半导体器件的方法，通过形成不对称的凹陷结构来改善化合物半导体器件的高频特性。 构成：通过顺序堆叠缓冲层（13），沟道层（14），间隔层（15），掺杂层（16），短键层（17），低密度掺杂 第一蚀刻停止层（19），第一欧姆层（20），第二蚀刻停止层和第二欧姆层（22）在半绝缘基板（12）上。 在形成用于形成欧姆电极的光致抗蚀剂图案之后，形成欧姆金属层，并通过进行热处理工艺形成源极/漏极的欧姆电极。 然后，通过使用栅极凹陷方法依次形成第一和第二阶梯式栅极凹部结构。 选择性地蚀刻低密度掺杂层（18）以形成第三非对称栅极结构。 然后，在该结构上沉积Ti / Pt / Au栅极金属电极（31）。 之后，通过使用剥离法去除光致抗蚀剂图案，以形成场效应型化合物半导体器件。

公开(公告)号：KR100261286B1

公开(公告)日：2000-07-01

申请号：KR1019970069507

申请日：1997-12-17

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 이재진 ,  김민건 ,  편광의

IPC: H01L21/20

Abstract: PURPOSE: A structure of an epitaxial substrate for a single chip microwave device is provided to improve the electrical characteristic of an interfacial surface and a metal by preventing an oxide layer from being formed in the interfacial surface between the epitaxial substrate and the metal. CONSTITUTION: A structure of an epitaxial substrate(1) comprises the first substrate including a buffer layer(2) having a thickness of 1 micrometer for obtaining the resistance higher than the resistance of the epitaxial substrate(1), an active layer(3) capable of forming a channel, and a cap layer(4) doped with impurities. The second substrate is formed on the first substrate. The second substrate includes the first metal layer(5), a dielectric layer(6) which is grown on the first metal layer(5), and the second metal layer(7) which is made of metal identical to the first metal layer(5). The dielectric layer(6) consists of AlAs so that the dielectric layer(6) can be formed through a sequence process.

Abstract translation: 目的：提供用于单芯片微波器件的外延衬底的结构，以通过防止在外延衬底和金属之间的界面表面中形成氧化物层来改善界面和金属的电特性。 构成：外延衬底（1）的结构包括第一衬底，其包括厚度为1微米的缓冲层（2），用于获得高于外延衬底（1）的电阻的电阻，有源层（3） 能够形成通道，以及掺杂有杂质的盖层（4）。 第二基板形成在第一基板上。 第二基板包括第一金属层（5），在第一金属层（5）上生长的介电层（6）和与第一金属层相同的金属制成的第二金属层（7） 5）。 电介质层（6）由AlAs组成，使得介电层（6）可以通过顺序工艺形成。

公开(公告)号：KR100251993B1

公开(公告)日：2000-04-15

申请号：KR1019970059227

申请日：1997-11-11

Applicant: 한국전자통신연구원

Inventor： 박병선 ,  이진희 ,  윤형섭 ,  편광의 ,  박철순

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a T-shaped gate conductive pattern by using a double-layered resist is provided to prevent the damage of a gate head caused by a backward scattering of exposure light and to obtain a minute gate foot. CONSTITUTION: In the method, the first and second resist used the double-layered resist are coated on a substrate. The second resist has a higher sensitivity to exposure light than the first resist has. Next, an exposure process using an exposure mask(400) and development process are performed in sequence to form a T-shaped opening in the double-layered resist. In particular, the exposure mask(400) has a gate foot pattern(401), a gate head pattern(402) and a dummy pattern(403) formed near an edge of the gate head pattern(402). The dummy pattern(403) only counterbalances the amount of an electron beam around the gate head without transferring any pattern. Thereafter, a conductive layer is formed over the double-layered resist having T-shaped opening. Next, by removing the double-layered resist, the T-shaped gate conductive pattern is obtained.

Abstract translation: 目的：提供通过使用双层抗蚀剂形成T形栅极导电图案的方法，以防止由于曝光光的反向散射而导致的栅极头的损坏并获得分钟栅极脚。 构成：在该方法中，将使用双层抗蚀剂的第一和第二抗蚀剂涂覆在基材上。 第二抗蚀剂比第一抗蚀剂具有比曝光光更高的灵敏度。 接下来，依次进行使用曝光掩模（400）和显影处理的曝光处理，以在双层抗蚀剂中形成T形开口。 特别地，曝光掩模（400）具有形成在栅极头图案（402）的边缘附近的栅极脚图案（401），栅极图案（402）和虚设图案（403）。 伪图案（403）仅在不转移任何图案的情况下均衡电子束在栅极头周围的量。 此后，在具有T形开口的双层抗蚀剂上形成导电层。 接下来，通过去除双层抗蚀剂，获得T形栅极导电图案。