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    IN-MEMORY PREPROCESSOR FOR A SCALABLE COMPOUND INSTRUCTION SET MACHINE PROCESSOR
    51.
    发明专利
    IN-MEMORY PREPROCESSOR FOR A SCALABLE COMPOUND INSTRUCTION SET MACHINE PROCESSOR 未知

    公开(公告)号：CA2038264C

    公开(公告)日：1995-06-27

    申请号：CA2038264

    申请日：1991-03-14

    Applicant: IBM

    Inventor： EICKEMEYER RICHARD J ,  VASSILIADIS STAMATIS ,  BLANER BARTHOLOMEW

    IPC: G06F15/00 ,  G06F9/00 ,  G06F9/38 ,  G06F13/38

    Abstract: A digital computer system capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.

    52.
    发明专利
    未知

    公开(公告)号：DE3750657T2

    公开(公告)日：1995-05-04

    申请号：DE3750657

    申请日：1987-12-18

    Applicant: IBM

    Inventor： BLANER BARTHOLOMEW

    IPC: H04L1/16 ,  H04L12/56 ,  H04L13/08 ,  H04L29/06 ,  H04L29/08

    Abstract: A first of a plurality of nodes in a multiprocessor system transmits a data packet to a second of the plurality of nodes over a data channel when the first node detects a predetermined sequence of bits on a control channel connected therebetween. The data packet is preceded on the data channel by a header which includes a plurality of fields informing the second node of the beginning of the data packet, the length of the data packet and the sequence number assigned to the packet. The data packet is followed by a field which enables the second node to determine whether the data packet was received correctly. If the second node determines that the data packet was received correctly, the data packet is stored in the node and an acknowledgement sequence is transmitted to the first node over the control channel. However, if an error occurs during the transmission of the data packet, the protocol enters an error state by removing all signal information from the data and control channels. Thereafter, a recovery processor, which is associated with each of the plurality of nodes, analyzes the state of the nodes at the time of the error in order to determine which corrective action needed to recover the respective node. The data link protocol also facilitates the transmission of a data packet from a first node through an intermediate node to a final node without storing the data packet in the intermediate node.

    Erzeugen einer dynamischen Huffman-Tabelle
    59.
    发明专利
    Erzeugen einer dynamischen Huffman-Tabelle 未知

    公开(公告)号：DE102016220801A1

    公开(公告)日：2017-05-18

    申请号：DE102016220801

    申请日：2016-10-24

    Applicant: IBM

    Inventor： ABALI BULENT ,  BLANER BARTHOLOMEW ,  FRANKE HUBERTUS ,  REILLY JOHN J

    IPC: H03M7/40

    Abstract: Bereitgestellt werden Methoden zum Erzeugen einer dynamischen Huffman-Tabelle in Hardware. Gemäß einem Aspekt beinhaltet das Verfahren zum Codieren von Daten die Schritte: Realisieren von dynamischen Huffman-Tabellen in Hardware, die eine Mehrzahl von Huffman-Baumformen repräsentieren, welche aus einem Beispieldatensatz vorberechnet werden, wobei die Huffman-Baumformen in den dynamischen Huffman-Tabellen durch Codelängenwerte repräsentiert werden; Schreiben von Symbolen und ihren Zählwerten aus den Eingabedaten in die dynamischen Huffman-Tabellen nach dem Empfang von Eingabedaten; Berechnen einer Wertung für jede der dynamischen Huffman-Tabellen mit den Symbolen und Zählwerten aus den Eingabedaten, wobei die Wertung auf den Codelängenwerten der vorberechneten Huffman-Baumformen und den Zählwerten aus den Eingabedaten beruht; und Auswählen einer gegebenen Tabelle aus den dynamischen Huffman-Tabellen, die eine niedrigste Wertung aufweist, für ein Codieren der Eingabedaten. Darüber hinaus wird ein Prozess zum Realisieren der vorliegenden Methoden in einem SRAM bereitgestellt.

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