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    5.
    发明专利
    未知

    公开(公告)号：DE69831906T2

    公开(公告)日：2006-06-14

    申请号：DE69831906

    申请日：1998-08-25

    Applicant: IBM

    Inventor： EISEN SUSAN ELIZABETH ,  PHILLIPS JAMES EDWARD

    IPC: G06F9/38

    Abstract: An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent "pipes" from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependencies between a computationally intensive floating point unit instruction (referred to as an fpu rr instruction) and the two previous computational intensive instructions having a target and a floating point register (the "fpr target") are tracked to provide a mechanism that quickly determines when dependent data is available from one of the floating point unit pipes. The data is then used to preempt the issue of a dependent instruction until data is available. Additionally, this out-of-order issue mechanism recognizes when consecutive instructions are dependent upon a same operand. In this situation, the mechanism prioritizes the first of the two instructions to be issued to the pipe satisfying the dependency, while the second instruction is preempted in favor of issuing an independent instruction or an instruction whose dependent data has already been made available to the other pipe when such an instruction is waiting in a queue.

    6.
    发明专利
    未知

    公开(公告)号：DE69831906D1

    公开(公告)日：2005-11-24

    申请号：DE69831906

    申请日：1998-08-25

    Applicant: IBM

    Inventor： EISEN SUSAN ELIZABETH ,  PHILLIPS JAMES EDWARD

    IPC: G06F9/38

    Abstract: An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent "pipes" from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependencies between a computationally intensive floating point unit instruction (referred to as an fpu rr instruction) and the two previous computational intensive instructions having a target and a floating point register (the "fpr target") are tracked to provide a mechanism that quickly determines when dependent data is available from one of the floating point unit pipes. The data is then used to preempt the issue of a dependent instruction until data is available. Additionally, this out-of-order issue mechanism recognizes when consecutive instructions are dependent upon a same operand. In this situation, the mechanism prioritizes the first of the two instructions to be issued to the pipe satisfying the dependency, while the second instruction is preempted in favor of issuing an independent instruction or an instruction whose dependent data has already been made available to the other pipe when such an instruction is waiting in a queue.

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