公开(公告)号：JP2000357394A

公开(公告)日：2000-12-26

申请号：JP2000131712

申请日：2000-04-28

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： KIRIHATA TOSHIAKI ,  GERHARD MUELLER

IPC: G11C11/401 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit device containing a redundant metal line that can replace a metal line in a non-operation state for connecting circuit blocks thereto. SOLUTION: A conductive data line in a non-operation state is decoupled to a circuit block to which the line is connected because of defect or the other reason. A conductive data line having defect is replaced by a redundant line by coupling the same circuit block. A spare conductive block is not required. This semiconductor integrated circuit device is provided with a circuit block 5, a conductor 4 coupled electrically to the circuit block, the other conductor 2 adapted so as to be coupled electrically to the circuit block, a first means 16, 18 for discriminating whether the conductor 4 is in an operation state or a non-operation state, a first switch 14 decoupling electrically the conductor 4 from a circuit block 5, and a second switch 12 for coupling the other conductor 2 to the circuit block 5.

公开(公告)号：JP2000312230A

公开(公告)日：2000-11-07

申请号：JP2000075093

申请日：2000-03-17

Applicant: IBM ,  SIEMENS AG

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD ,  HANSON DAVID R

IPC: H03K19/0175 ,  G06F13/28 ,  G11C7/10 ,  G11C11/407 ,  H04L25/02 ,  H04L25/03

Abstract: PROBLEM TO BE SOLVED: To provide a dynamic latch receiver circuit that latches a burst mode data signal in a way of avoiding a low pass filter effect for global pointer transfer. SOLUTION: This circuit 100 includes a series of data latch circuits 138a-138d that are laid out in parallel and attain sequential latch of a data signal sequentially transmitted on a signal data line 14, includes a 1st signal generator that generates 1st pointer signals 122a-122s each of which corresponds to a specific latch circuit and is overlapped temporally with the 1st pointer signal generated precedingly and pulse converters 148 (148a...) and 158 (158a...) that receive the corresponding 1st pointer signal and generates a 2nd pointer signal to be given to the respective latch circuits. Each of the 2nd pointer signals is generated according to a sequence where no overlapping takes place and triggers latching of each data signal.

公开(公告)号：JP2000251471A

公开(公告)日：2000-09-14

申请号：JP2000046381

申请日：2000-02-23

Applicant: IBM

Inventor： JI BRIAN ,  KIRIHATA TOSHIAKI ,  DIMITRI NETIS

IPC: G11C11/407 ,  G11C7/00 ,  G11C11/401 ,  G11C11/408 ,  G11C11/4097

Abstract: PROBLEM TO BE SOLVED: To activate a word line in a hierarchical form by equalizing the number of timing-critical address lines to the number of banks, and connecting plural exclusive address lines to respective one of each block. SOLUTION: After a first bank is decoded using a timing signal of a signal line 300, a timing signal of the signal line 300 is transferred, a single memory block 330 is decoded in the bank, lastly, a single word line WL is activated, and the third decoding is performed by a shared row decoder/word line driver 61. At the beginning, a pre-decoded address signal of the signal line 300 including timing information is used at a first level of hierarchical decoding, after a single bank of a unit is activated, an address signal in the signal line 300 is multiplexed with other addresses pre-recorded statically in a signal line 310 having possibility for continuous variation independently of a bank address.

公开(公告)号：JPH11317507A

公开(公告)日：1999-11-16

申请号：JP36124698

申请日：1998-12-18

Applicant: SIEMENS AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To enable master bit lines to be enhanced in pitch and lessened in line capacitance, by a method wherein the master bit lines are set shorter than a row length, and some of the master bit lines covering memory cells are set larger than local bit lines in pitch. SOLUTION: Master bit lines MBL are interleaved, and the master bit lines MBL are shortened to be half or below as long as a row, whereby the master bit lines MBL can be set wider in pitch than those of conventional technique architecture. All the capacitance of the master bit lines MBL gets smaller with a reduction in the length of the master bit line and with an increase in a space between the adjacent master bit lines. As a space is increased, inter-bit line capacitance between the adjacent master bit lines MBL is decreased, so that all the capacitance of the master bit lines MBL becomes small. When the master bit lines MBL are widened in pitch, DRAMs are improved in yield.

公开(公告)号：JPH11317093A

公开(公告)日：1999-11-16

申请号：JP7746699

申请日：1999-03-23

Applicant: IBM ,  TOSHIBA CORP

Inventor： KIRIHATA TOSHIAKI ,  DEBROSSE JOHN K ,  WATANABE YOJI ,  WONG HING

IPC: G11C29/04 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide the method and the device to restore a semiconductor memory device. SOLUTION: In order to simultaneously substitute a normal true word line and normal auxiliary word line pairs Ui and Uj , a row redundancy substituting device, which consists of a redundancy true word line and redundancy auxiliary word line pairs RUk and RU2 , is provided. While conducting the restoration, which is executed as a word line selector circuit 506 using the address rearranging system controlled by a redundancy control logic 508 and an address input 510, a normal true (auxiliary) word line is substituted by a redundancy true (auxiliary) word line. In the redundancy replacing device, the consistency in a bit map is always maintained regardless of whether the memory device is operated in a normal mode or a redundancy mode.

公开(公告)号：JPH11317077A

公开(公告)日：1999-11-16

申请号：JP1809599

申请日：1999-01-27

Applicant: IBM

Inventor： HOSOKAWA KOHJI ,  KIRIHATA TOSHIAKI

IPC: G11C11/407 ,  G11C8/10 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To provide a plural bank memory structure in a double unit so as to conduct a column address incrementing pipeline process in each bank. SOLUTION: The memory system includes a physically continuous storage unit 310, which is address specified as plural column regions and at least one row region, a row selection unit 312, which activates selected word line of a row region whole body in response to a row address, a first column selection unit 329a, which activates a first selected bit line pair in a first column region 314 in response to a column address, a means 322a, which increments a column address, and a second column selection unit 328a which activates a second selected bit line pair in a second column region in response to the incremented column address. Thus, the first and the second selected bit line pairs are activated and the storage place of a continuous storage unit is accessed.

公开(公告)号：JPH11273344A

公开(公告)日：1999-10-08

申请号：JP1816399

申请日：1999-01-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： JI BRIAN L ,  KIRIHATA TOSHIAKI

IPC: G11C11/407 ,  G11C8/10 ,  G11C11/401 ,  G11C11/409

CPC classification number: G11C8/10

Abstract: PROBLEM TO BE SOLVED: To obtain a common row decoder and a common row decoding method for supplying selection signals independently timing-controlled of each other to a first memory unit and a second memory unit, respectively.
SOLUTION: A common row decoder 110 includes an address input circuit 111 for supplying an enable input or a disable input in response to conditions of address signals XPs. Furthermore, a first and second selection circuits are provided for supplying selection signals RDOUT independently timing-controlled of each other to the first and second memory units, respectively, in response to first and second block selection inputs BLKSEL, enable conditions of first and second timing signals RDECON, and the enable input of the address input circuit.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：为了获得共同的行解码器和公共行解码方法，分别将第一存储单元和第二存储单元独立地进行定时控制的选择信号。 解决方案：公共行解码器110包括地址输入电路111，用于响应于地址信号XPs的条件提供使能输入或禁止输入。 此外，提供第一和第二选择电路，用于响应于第一和第二块选择输入BLKSEL，分别为第一和第二存储器单元提供彼此独立地定时控制的选择信号RDOUT，使第一和第二定时的使能条件 信号RDECON和地址输入电路的使能输入。

公开(公告)号：JPH1196799A

公开(公告)日：1999-04-09

申请号：JP19140198

申请日：1998-07-07

Applicant: IBM ,  SIEMENS AG

Inventor： KIRIHATA TOSHIAKI ,  GEEBURIERU DANIERU ,  JIYAN MAAKU DORUTEYU ,  KAARU PEETAA PUFUETSUFUERU

IPC: G06F12/16 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To make a memory of arbitrary size fault tolerant by enabling using an effective replacement domain out of at least two variable domains in which one part is overlapped. SOLUTION: Capacitive electric charges from a capacitor 25 on a bit line BL is amplified by a sense amplifier 28, selected as bit information by a corresponding column address, and sent to a data output circuit. A 256K redundant block including RWL of 128 lines is used for each 16Mb primary array 19 instead of a redundant word line RWL in each 1Mb block. A redundant block 22 includes RU 0-63 of 64 pieces. One 1MB domain A is related to each of RU 0-15, RU 16-31 are used with 4Mb domain B, residual R32-R63 are related to whole replacement domain C. The most effective and efficient domain selection can be performed in an obstacle type so that domain A-C are overlapped one another, at unit restorable possibility is improved at the time of hard obstacle and holding obstacle.

公开(公告)号：JPH1131399A

公开(公告)日：1999-02-02

申请号：JP10072198

申请日：1998-04-13

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  WAIT CHRISTOPHER

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/273 ,  G11C29/12 ,  H01L21/66 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit chip and an electronic system in which a self-test system is incorporated, respectively. SOLUTION: An integrated circuit chip 1 comprises a function of a built-in self-test(BIST) and a non-volatile memory, and a BIST 2 can use a self-program. An electronic system comprises an integrated circuit chip including on-chip built-in self-test(BIST) and a non-volatile memory as well as an off(3)hip test target. The integrated circuit chip and the electronic system are especially useful to simplify a test of an electronic product in both of manufacturing and an actual site, necessity of a tester having a large size, complexity, and high speed in manufacturing environment is dissolved, and the system is made useful further when a simple electric power chuck is used instead of inserting a product.

公开(公告)号：JPH10214133A

公开(公告)日：1998-08-11

申请号：JP36071497

申请日：1997-12-26

Applicant: SIEMENS AG ,  IBM

Inventor： WONG HING ,  KIRIHATA TOSHIAKI ,  KRSNIK BOZIDAR

IPC: G06F1/06 ,  G01R31/30 ,  G06F1/08 ,  G11C7/22

Abstract: PROBLEM TO BE SOLVED: To provide an external control means for accelerating efficient circuit design relating to a test mode for controlling the timing of the internal signals of an integrated circuit by leading out internal control signals from external signals and supplying the external signals to the external pin of the integrated circuit at the time of the test mode. SOLUTION: The control circuit is provided with two operating modes, that are a normal mode and a test mode. In the normal mode, a normal signal route is used for the timing control of the internal signals 40. The normal signal route is provided with a sub circuit 5 and the sub circuit 5 is operated by the internal signals 21 and forms output signals 31. In the test mode, a test mode signal route is used for the timing control of the internal signals 40 and the test mode signal route is provided with the sub circuit 10. By the operation of the test mode signal route, the output signals 36 of the sub circuit 10 are led out from the external signals 26. The external signals 26 are supplied to the external pin of the integrated circuit.