51.
    发明专利
    未知

    公开(公告)号:DE10121578A1

    公开(公告)日:2002-11-14

    申请号:DE10121578

    申请日:2001-05-03

    Abstract: The invention relates to a method and a component system (4) for providing a substrate (1) with an electronic component (2). The component system (4) comprises a substrate carrying device (5) for receiving the substrate, a wafer carrying device (6) placed over the substrate carrying device (5) for receiving a wafer carrying frame (10), as well as a vacuum pincette-holder device (7) placed above the wafer carrying device (6). The wafer carrying frame (10) can receive a complete semiconductor wafer (3) divided into electronic components.

    53.
    发明专利
    未知

    公开(公告)号:DE10023869A1

    公开(公告)日:2002-01-17

    申请号:DE10023869

    申请日:2000-05-16

    Inventor: HOEGERL JUERGEN

    Abstract: A circuit configuration for reliably and simply interconnecting circuit modules includes a connection carrier and circuit modules disposed essentially one above another approximately in a stack. Each of the circuit modules has a connecting device for externally and electrically bonding the circuit modules. The connecting device has at least one series configuration of connecting elements disposed essentially in a plane. The connecting elements are disposed on the connection carrier. The connecting device of at least one of the circuit modules is at least partially electrically connected to another connecting device of at least one different one of the circuit modules in direct mechanical and electrical contact.

    54.
    发明专利
    未知

    公开(公告)号:DE10017741A1

    公开(公告)日:2001-10-25

    申请号:DE10017741

    申请日:2000-04-10

    Abstract: A housing for semiconductor chips includes a plastic base substrate having a region for accommodating a chip and substrate sides having a patterned metallization layer. One of the sides contacts a chip and another contacts an external electrical connection. Each chip has front and rear sides and at least one chip contact on each side. Two or more pads are formed in the patterned metallization layer on one of the base substrate sides. One of the pads is connected to a front side chip contact and another is connected to a rear side chip contact. At least one pad is formed in the patterned metallization layer on the other base substrate side and is connected to the external electrical connection. One of the two pads is connected to a chip contact through the bonding wire, and another of the two pads is directly applied to another chip contact.

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