公开(公告)号：DE10330812A1

公开(公告)日：2005-04-14

申请号：DE10330812

申请日：2003-07-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS ,  RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM

IPC: G06F12/00 ,  G06F13/16 ,  G11C5/06 ,  G11C7/10 ,  G11C11/41

公开(公告)号：DE10345384B3

公开(公告)日：2005-03-24

申请号：DE10345384

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM ,  MUFF SIMON

IPC: G11C5/00 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/0185 ,  G11C7/10

Abstract: The system has a device (102) for controlling first and second circuit units (104,106) with a differential control signal with a first control signal and a second control signal inverted relative to the first and a differential control signal line (120) with first and second lines (122,124) for carrying the first and second control signals. The first and second circuit units are connected to the control device via the first and second signal lines respectively. .

公开(公告)号：DE10345550B3

公开(公告)日：2005-02-10

申请号：DE10345550

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  KALMS SVEN ,  KUZMENKA MAKSIM ,  HAUSMANN MICHAEL

IPC: G11C7/10 ,  G11C8/12 ,  G11C11/4096

Abstract: The memory device has an even number of at least 4 random-access memory modules (D), each having a given number of memory cells organized in disjunctive cell groups, the cells in each group simultaneously selected by a cell group address for write-in or read-out of data via a m-bit data bus (DB), connected to an n-bit parallel port (DP) via a data register (DR). The memory modules are divided into at least 2 disjunctive module groups with the least possible difference in their spacings from the data register, a selection device (SR,DS,AB,A) used for selection of a module from the same module group for each m-bit group of the same n-bit packet.

公开(公告)号：DE10318603A1

公开(公告)日：2004-12-09

申请号：DE10318603

申请日：2003-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUZMENKA MAKSIM ,  RUCKERBAUER HERMANN

IPC: G06F1/04 ,  H03K5/15 ,  H03M9/00

Abstract: Circuit generated output signals are to be processed by lower detecting speed. Circuit comprises input (10) for high speed input signal (Data) and number of integration elements (C1-C4). Switch (S1) connects input to one of elements for its integration. Numerous appliances (60,62,64,66) receive each one integrated signal and transmits one of number of numerous output signals. Switch is separately controlled so that high speed input signal in each subsequent input clock interval is integrated in another integration element. Independent claims are included for data memory and reception method.

公开(公告)号：DE10229167B3

公开(公告)日：2004-02-19

申请号：DE10229167

申请日：2002-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKENBAUER HERMANN ,  KUZMENKA MAKSIM

IPC: H01R12/18 ,  H01R12/16 ,  H01R12/71 ,  H05K1/11 ,  H01R13/631 ,  H01R13/11 ,  H01R13/703

Abstract: The fixing and contacting device uses signal lines (32) applied to the surface of the substrate (3) provided with contact zones (34) and a plug-in mounting device (1) for reception of the component module (2), having contact elements (7) spaced from the signal line contact zones before insertion of the component module and deformed upon insertion of the component module, for providing an electrical connection between the component module contacts (6) and the signal line contact zones. Also included are Independent claims for the following: (a) a plug-in mounting for fixing and contacting a component module mounted on a substrate; (b) a contact element for a plug-in mounting device

公开(公告)号：DE10229170A1

公开(公告)日：2004-01-29

申请号：DE10229170

申请日：2002-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM

IPC: H01R13/703

Abstract: A plug-in connector (1) has at least one receptacle (5) for receiving a switching module provided with a contact device (23) and a number of signal-carrying (71) and signal-removing (71') contacts corresponding to the contact device (23). In the equipped state, the contacts (71,71) are connected with the corresponding contact devices (23) and in the un-equipped state at least one signal-carrying contact (71) is electrically connected with one signal-removing contact (71').

公开(公告)号：DE10157874A1

公开(公告)日：2003-06-12

申请号：DE10157874

申请日：2001-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUZMENKA MAKSIM

IPC: G06F13/00 ,  G06F13/14 ,  G11C5/00 ,  G11C7/22 ,  G11C8/06

Abstract: A device for supplying control signals to memory units of a memory module comprises a first bus section for supplying a first part of the control signals to a first memory unit. In addition, a second bus section is provided for supplying a second part of the control signals to a second memory unit. Finally, the device comprises redrive means for redriving the first part of the control signals from the first memory unit to the second memory unit and for redriving the second part of the control signals from the second memory unit to the first memory unit. A memory unit for such a device for supplying control signals comprises first inputs for receiving a first part of the control signals from a memory control, second inputs for receiving a second part of the control signals from at least one other memory unit, and outputs for redriving said first part of the control signals to said at least one other memory unit.

公开(公告)号：DE10153752A1

公开(公告)日：2003-05-28

申请号：DE10153752

申请日：2001-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUZMENKA MAKSIM

IPC: G11C7/10 ,  G11C8/04 ,  G06F12/00 ,  G06F13/16

Abstract: The access registers (50,52) are arranged between the groups of registered memory units (1-3,4-6,7-9) such that the outputs (54,78) of register (50) are partially connected to inputs of both the memory groups (1-3,4-6) and the outputs (56,82) of register (52) are partially connected to inputs of both the memory groups (4-6,7-9). An Independent claim is also included for access register.

公开(公告)号：DE10153751A1

公开(公告)日：2003-05-28

申请号：DE10153751

申请日：2001-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUZMENKA MAKSIM

IPC: G11C7/22 ,  H03K5/00 ,  H03K5/08 ,  H03K5/13 ,  H03L7/00

Abstract: The clock generator has an interface (24) for receiving n periodic signals having the same frequency. The signals are phase-shifted with respect to each other. A clock signal generator (26) generates respective clock edges of the signals if two of the phase-shifted signals satisfy a predetermined relationship. The frequency of the generated clock signal is n or 2n times that of the phase-shifted signals. An Independent claim is also included for a method for generating a clock signal.