公开(公告)号：JP2002093146A

公开(公告)日：2002-03-29

申请号：JP2001201320

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOHM THOMAS ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide an MRAM assembly permitting to reduce an area necessary for line drive circuits by their effective arrangement and permitting space- saving design. SOLUTION: Word line drive circuits (6, 7) are assigned to two memory cell arrays (1, 2 or 2, 3) via each connecting node (4, 5) so that the drive circuit area is substantially reduced by half.

公开(公告)号：JP2002124080A

公开(公告)日：2002-04-26

申请号：JP2001235533

申请日：2001-08-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C5/06 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a device performing write-in in which loss of MRAM is less and in which memory cells having large resistance, short word lines and/or bit lines are not utilized. SOLUTION: This device has many memory cells (Z0, Z1, etc.), and these memory cells are provided respectively in a memory cell field between a word line(WL) and bit lines (BL, BL0, BL1, etc.). At the time of write-in process for the prescribed memory cell, voltage drop (V1-V2) is caused in the selected word line(WL) connected to this memory cell. When voltage V1 or voltage V2

公开(公告)号：JP2001351376A

公开(公告)日：2001-12-21

申请号：JP2001106108

申请日：2001-04-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESTERL ROBERT ,  HONIGSCHMID HEINZ ,  KANDOLF HELMUT ,  ROEHR THOMAS

IPC: G11C11/22

Abstract: PROBLEM TO BE SOLVED: To provide an operation method for integrated memory in which attenuation or damage of information stored in a memory cell is prevented. SOLUTION: Colum lines and substrate lines connected to a selected memory cell have an initial potential before being accessed, and activate row lines connected to the selected memory cell during one access, thereby, switch a selection transistor of the selected memory cell to be in a conduction state, apply a potential being different from a potential of a column line to the substrate line, evaluate and amplify potentials applied to the column lines at a first point of time, successively, apply the initial potential to the substrate line at a second point of time, successively, apply the initial potential to column lines at a third point of time. The first point of time, the second point of time, and the third point of time are selected so that a memory capacitor of the selected memory cell is charged and discharged by the same quantity every time.

公开(公告)号：JP2001283585A

公开(公告)日：2001-10-12

申请号：JP2001030127

申请日：2001-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESTERL ROBERT ,  KANDOLF HELMUT ,  HONIGSCHMID HEINZ ,  ROEHR THOMAS

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105

Abstract: PROBLEM TO BE SOLVED: To prevent change of memory contents caused by faulty voltage by connecting a column line and a charging line to a connection terminal 22 of a common power feeding potential GND in a non-active operation mode and in a common read-out amplifier or a driver circuit. SOLUTION: This integrated semiconductor memory is provided with a memory cell field having a ferroelectric memory effect memory cell MC, row lines WL1, and column lines BL1, the memory cell is inserted between one column line and a charging line PL1, the column line is connected to a read-out amplifier 2 from which an output signal S21 is taken, the charging line is connected to the driver circuit 3 connecting the amplifier 2 to a potential V1 and GND. and the column line and the charging line have an activation or a non-activation mode.

公开(公告)号：WO0167248A3

公开(公告)日：2001-12-20

申请号：PCT/EP0101939

申请日：2001-02-21

Applicant: INFINEON TECHNOLOGIES AG ,  BOEHM THOMAS ,  KANDOLF HELMUT ,  LAMMERS STEFAN ,  MANYOKI ZOLTAN

Inventor： BOEHM THOMAS ,  KANDOLF HELMUT ,  LAMMERS STEFAN ,  MANYOKI ZOLTAN

IPC: G11C29/04 ,  G11C29/24 ,  G11C29/46 ,  G06F11/20 ,  G11C29/00

CPC classification number: G11C29/24 ,  G11C29/46

Abstract: The invention relates to a digital memory circuit with a memory matrix (50), comprising M regular rows and N regular columns and, furthermore, P

Abstract translation: 本发明涉及一种具有存储器矩阵（50）中，M个常规的行和N包含常规列，并且还P

公开(公告)号：DE10332449A1

公开(公告)日：2004-12-09

申请号：DE10332449

申请日：2003-07-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAUSMANN MICHAEL ,  KANDOLF HELMUT ,  KALMS SVEN

IPC: G06F5/06 ,  G06F5/08 ,  G11C8/04

Abstract: First-in first-out (FIFO) shift register has register elements each with a memory element of a masking memory for storage of a valid datum with first or second validity information. Register element and memory element are connected in such a way that when a read access is made to the memory element, the datum is shifted to the next register element.

公开(公告)号：DE10146491A1

公开(公告)日：2003-04-24

申请号：DE10146491

申请日：2001-09-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  BRAUN GEORG

IPC: H03K19/00 ,  H04L25/06 ,  H04L12/40 ,  H04B3/04

Abstract: An electronic circuit has a driver circuit to drive a signal onto a signal line. The driver circuit contains a first switching device with a first forward resistance between a first supply voltage terminal and the signal line, and a second switching device with a second forward resistance between a second supply voltage terminal and the signal line. A control circuit is provided to generate a first and a second control signal to control the first and second switching devices in a first operating mode such that, depending on the signal which is to be driven, either the first switching device or the second switching device is through-connected. In a second operating mode, the first switching device and the second switching device are essentially through-connected with the aid of the first and second control signals so that the first and second forward resistances together form a terminating resistance.

公开(公告)号：DE10140344A1

公开(公告)日：2003-03-06

申请号：DE10140344

申请日：2001-08-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE ,  NIKUTTA WOLFGANG ,  BORCKE MATHIAS VON ,  KANDOLF HELMUT

IPC: H03K5/01 ,  H03K17/16 ,  H03K17/693 ,  H03K5/12 ,  H03K6/04

Abstract: The signal driver (100) has a first unit (102) for driving the signal (Vout) from first level in direction to a second level and a line of intermediate levels, contg. an intermediate level different from a reference level. The reference level lies between the first and second signal levels. A second unit (106) drives the signal in the direction of the second signal level from the last intermediate level of the line of intermediate levels. Independent claims are included for integrated circuit contg. the signal driver.

公开(公告)号：DE10062570C1

公开(公告)日：2002-06-13

申请号：DE10062570

申请日：2000-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR

IPC: G11C8/12 ,  G11C11/15 ,  G11C11/14

Abstract: The read and write control circuit has selection transistors provided for each bit line (BL) on both sides of each memory cell connected to respective pairs of read/write amplifiers (AMPH,AMPL) at the bit line ends, each having a current source and a current drain. The read/write amplifiers respond to a write signal, to provide a write current in one or other direction for write-in of a logic 0 or 1 for all bit lines selected by a column select signal applied to a column select line (CS), with read out of the logic 0 or 1 by application of a read signal to a selected memory cell. An Independent claim for a magnetoresistive memory is also included.

公开(公告)号：DE10010456B4

公开(公告)日：2005-10-27

申请号：DE10010456

申请日：2000-03-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ ,  LAMMERS STEFAN

IPC: G11C11/22 ,  G11C5/14 ,  G11C7/18 ,  G11C8/14 ,  G11C11/4097 ,  G11C16/28 ,  H01L27/115