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公开(公告)号：JP2006351014A
公开(公告)日：2006-12-28
申请号：JP2006164490
申请日：2006-06-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WEIS CHRISTIAN , KALMS SVEN , RUCKERBAUER HERMANN
Abstract: PROBLEM TO BE SOLVED: To provide a memory device having an ECC function further easily understandable and having a simple architecture. SOLUTION: This memory device is provided with at least two DRAM memory modules, at least one external ECC module and a memory controller. The external ECC module provides the ECC function to the memory modules. The respective memory modules are connected to the memory controller through memory channels corresponding to them. The plurality of external ECC modules are connected to the memory controller through one shared ECC channel. Each external ECC module is allocated to one group comprising the plurality of memory modules. The plurality of memory modules of the one group having the respective ECC modules are operated in synchronization with one another by the memory controller. COPYRIGHT: (C)2007,JPO&INPIT
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公开(公告)号：DE10332449A1
公开(公告)日：2004-12-09
申请号：DE10332449
申请日：2003-07-17
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HAUSMANN MICHAEL , KANDOLF HELMUT , KALMS SVEN
Abstract: First-in first-out (FIFO) shift register has register elements each with a memory element of a masking memory for storage of a valid datum with first or second validity information. Register element and memory element are connected in such a way that when a read access is made to the memory element, the datum is shifted to the next register element.
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Patent Agency Ranking
公开(公告)号：DE102005046134A1
公开(公告)日：2007-04-12
申请号：DE102005046134
申请日：2005-09-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WEIS CHRISTIAN , KALMS SVEN
Abstract: Electronic component group (10) comprises electronic components (1-4) connected in series so that a number of input connections (11) of one component is connected to a number of output connections (12) of another component. The input connections and the output connections are arranged in the same geometric arrangement. An independent claim is also included for a method for transmitting information in electronic components. Preferred Features: Each electronic component is a rank of a digital memory. The geometric is mirror-symmetrical and/or rotation-symmetrical.
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公开(公告)号：DE102006021363A1
公开(公告)日：2006-12-28
申请号：DE102006021363
申请日：2006-05-08
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WEISS CHRISTIAN , KALMS SVEN , RUCKERBAUER HERMANN
Abstract: The device has two dynamic RAM memory modules (1) and external error correcting code (ECC) modules providing memory modules with ECC functionality. A memory controller (2) is arranged and the memory modules are connected to the controller by memory channels. The ECC modules are attached at the controller over a common ECC channel. The memory modules are operated synchronously with corresponding ECC modules by the controller.
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公开(公告)号：DE10328658A1
公开(公告)日：2005-02-10
申请号：DE10328658
申请日：2003-06-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KALMS SVEN , KANDOLF HELMUT
Abstract: One embodiment of the invention provides a hub chip comprising: an address bus input for receiving a plurality of successively sent portions of address and/or command data, a shift register which has register elements and is connected to the address bus input to receive the plurality of portions of the address and/or command data, the shift register being connected to the address bus input so that, when the address and/or command data are received, the portions of the address and/or command data are successively written to the register elements, an address bus output for outputting the received address and/or command data, a memory module interface for connecting one or more memory modules, where the hub chip addresses none, one or a plurality of the connected memory modules, depending on the address and/or command data transferred, and a driver element provided to output the received portion of the address and/or command data to the address bus output before all of the portions of the address and/or command data have been received in full.
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公开(公告)号：DE102006021363B4
公开(公告)日：2015-08-13
申请号：DE102006021363
申请日：2006-05-08
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WEISS CHRISTIAN DR , KALMS SVEN , RUCKERBAUER HERMANN
Abstract: Speichervorrichtung mit: – wenigstens zwei DRAM-Speichermodulen (1); – wenigstens einem externen ECC-Modul (5), das die Speichermodule (1) mit ECC-Funktionalität ausrüstet, und – einem Speicher-Controller (2), wobei: – die Speichermodule (1) an den Speicher-Controller (2) über entsprechende Speicherkanäle (3) direkt angeschlossen sind, – das wenigstens eine externe ECC-Modul (5) an den Speicher-Controller (2) über einen gemeinsamen ECC-Kanal (6) direkt anschließbar und einer Gruppe (A, B) von Speichermodulen (1) zugeordnet ist und – die Speichermodule (1) von einer der Gruppen (A, B) mit dem entsprechenden wenigstens einen ECC-Modul (5) synchron über den Speicher-Controller (2) betreibbar sind, so dass die Ressourcen des wenigstens einen externen ECC-Moduls voll genutzt sind.
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公开(公告)号：DE10345550B3
公开(公告)日：2005-02-10
申请号：DE10345550
申请日：2003-09-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KANDOLF HELMUT , KALMS SVEN , KUZMENKA MAKSIM , HAUSMANN MICHAEL
IPC: G11C7/10 , G11C8/12 , G11C11/4096
Abstract: The memory device has an even number of at least 4 random-access memory modules (D), each having a given number of memory cells organized in disjunctive cell groups, the cells in each group simultaneously selected by a cell group address for write-in or read-out of data via a m-bit data bus (DB), connected to an n-bit parallel port (DP) via a data register (DR). The memory modules are divided into at least 2 disjunctive module groups with the least possible difference in their spacings from the data register, a selection device (SR,DS,AB,A) used for selection of a module from the same module group for each m-bit group of the same n-bit packet.
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