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    Integrated circuit for analysis of input signal characteristics has one port for first input signal, which adopts first and second state during first signal period and another port for second input signal
    52.
    发明专利
    Integrated circuit for analysis of input signal characteristics has one port for first input signal, which adopts first and second state during first signal period and another port for second input signal 未知

    公开(公告)号：DE102004059447A1

    公开(公告)日：2006-06-14

    申请号：DE102004059447

    申请日：2004-12-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHAMBERGER FLORIAN ,  KAISER ROBERT

    IPC: G11C7/10 ,  G11C11/407

    Abstract: Integrated circuit has one port (T1) for first input signal (CLK), which adopts first and second state during first signal period and another port (T2) for second input signal (bCLK). First memory circuit (10) stores first state of second input signal and second memory circuit (20) stores the first state of second input signal. Input side (SHin) of first memory circuit is linked to port of second input signal and input side of second memory circuit is linked to port of second input signal. First memory circuit is designed such that input side of first memory circuit stored the first state of second input signal in it during delivery period of first state of second input signal. Second memory circuit is designed such that input side of second memory circuit stored the input state of second input signal in it during delivery period of second state of first input signal. Current evaluation circuit (40) for the generation of evaluating signal (AS) stored state (S1) of second input signal in first memory circuit. Current evaluation circuit is designed such that output side (A40) is generated by evaluating signal and state of second input signal is stored in first memory circuit and state (B1) of second input signal is stored in second memory circuit distinctively. Current evaluation circuit is designed such that output side is generated by evaluating signal and state of second input signal is stored in first memory circuit and state of second input signal is stored in second memory circuit, which is coinciding. An independent claim is also included for method of analysis of input signal characteristic of an integrated circuit.

    53.
    发明专利
    未知

    公开(公告)号：DE10117614B4

    公开(公告)日：2005-06-23

    申请号：DE10117614

    申请日：2001-04-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

    IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

    Abstract: A data read access and a data write access is shared between two memory banks. A first memory bank of which is operated with a clock that is shifted by half a clock pulse with respect to the operating clock of the other, second memory bank. Partial data streams are combined at the output of the two memory banks to form a data stream with double the frequency.

    55.
    发明专利
    未知

    公开(公告)号：DE10115614C2

    公开(公告)日：2003-12-18

    申请号：DE10115614

    申请日：2001-03-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

    IPC: G11C5/14 ,  G11C29/12 ,  H01L23/58 ,  G11C29/00 ,  H01L21/66 ,  H01L23/525

    Abstract: A method for supplying current to a semiconductor chip, particularly to a semiconductor memory chip, in which, in a standby mode, the semiconductor chip is supplied with current from a standby current generator, and in which, in a normal operating mode, the semiconductor chip is supplied with current from a normal mode current generator. The standby current generator provides a smaller current than the normal mode current generator, and where, in a product development phase, the semiconductor chip is supplied with current from the standby current generator in a test mode. The semiconductor chip is additionally to be supplied with current from the normal mode current generator in the product development phase.

    56.
    发明专利
    未知

    公开(公告)号：DE59905800D1

    公开(公告)日：2003-07-10

    申请号：DE59905800

    申请日：1999-07-01

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KRASSER HANS-JUERGEN ,  SCHAMBERGER FLORIAN

    IPC: G01R31/3187 ,  G06F11/00 ,  G06F11/22 ,  G11C29/00 ,  G11C29/12 ,  G11C29/44

    Abstract: An arrangement for storing test results obtained with a BIST-circuit (7) (built-in self-test circuit) from a semiconductor chip (1) provided with a memory or storage device (2-5), operates by the self-storable test results being saved in the read amplifiers (6) of the storage or memory device. The test programs for the BIST-circuit (7) are specifically stored in the read amplifiers (6), and the test results are more specifically stored in the read amplifier (6) of the storage device (2-5).

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